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altera corporation section i?1 preliminary section i. hardcopy ii device family data sheet this section provides designers wi th the data sheet specifications hardcopy ? ii devices. these cpaters contain feature definitions of the internal architecture, configuration and jtag boundary-scan testing information, dc operationg cond itions, ac timing parameters, a reference to power consumption, and ordering information for hardcopy ii devices. this section contains the following: ?introduction to hardcopy ii devices? on page 1?1 ?description, architecture, and features? on page 2?1 ?boundary-scan support? on page 3?1 ?dc and switching specifications and operating conditions? on page 4?1 ?quartus ii support for hardcopy ii devices? on page 5?1 ?script-based design for hardcopy ii devices? on page 6?1 ?timing constraints for hardcopy ii devices? on page 7?1 ?migrating stratix ii device resources to hardcopy ii devices? on page 8?1 revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the complete handbook.
section i?2 altera corporation preliminary revision history hardcopy series handbook, volume 1
altera corporation 1?1 september 2008 preliminary 1. introduction to hardcopy ii devices introduction hardcopy ? ii devices are low-cost, high -performance structured asics with pin-outs, densities, and architecture that complement stratix ? ii devices. hardcopy ii device features, such as phase-locked loops (plls), memory, and i/o elements (ioes), ar e functionally and electrically equivalent to the stratix ii fpga features. the combination of stratix ii fpgas for in-system prototype and design verification, hardcopy ii devices for high-volume pr oduction, and the quartus ? ii software for design, provide a complete, low-risk design solution. hardcopy ii devices improve on the successful and proven methodology of the two previous generations of hardcopy series devices. altera ? hardcopy ii devices use the same base arrays across multiple designs for a given device density and are customized using only two metal layers. hardcopy ii devices offer up to 90% cost reduction compared to stratix ii fpga prototypes. the quartus ii software provides a complete set of tools, common for both designing stratix ii fpga pr ototypes and for quickly migrating the design to a hardcopy ii companion de vice. hardcopy ii devices are also supported through other front-en d design tools from synopsys, synplicity, and mentor graphics ? . feature overview hardcopy ii structured asics are manufactured on a 1.2 v, 90 nm all-layer-copper metal fabrication process (up to nine layers of metal). hardcopy ii devices offer the following features: fine-grained hcell architecture resulting in a low-cost, high-performance, low-power structured asic customized using only two metal la yers for fast turn-around times and low non-recurring expenses (nre) fully tested prototypes are available in approximately 10 to 12 weeks from the date of your design submission support for instant-on or instant-on-after-50-ms power-up modes preserves the design functionalit y of a stratix ii fpga prototype 1,000,000 to 3,600,000 usable gates fo r both logic and dsp functions h51015-2.6
1?2 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 system performance up to 350 mhz up to 50% power reduction (dynamic and static) for typical designs compared to stratix ii fpga prototypes 1 the actual performance and po wer consumption improvements mentioned in this datasheet are design-dependent. internal memory up to 8,847,360 ram bits availabl e (including parity bits) true dual-port memory, suitable for use in first-in-first-out (fifo) buffers phase-locked loops (plls) up to 16 global clocks with 24 clocking resources per device region clock control block supports dynamic clock network enable/disable and dynamic gl obal clock network source selection up to 12 plls (four enhanced plls and eight fast plls) per device which provide identical features as the fpga counterparts, including spre ad spectrum, programmable bandwidth, clock switchover, real-time pll reconfiguration, advanced multiplication, and phase shifting i/o standards and intell ectual property (ip) support for numerous single-ended and differential i/o standards such as lvttl, lvcmos, pci, pci-x, sstl, hstl, and lvds high-speed differential i/o support on up to 116 channels with dynamic phase alignmen t (dpa) circuitry for 1-gigabit-per-second (gbps) performance support for high-speed networking and communications bus standards including parallel rapidio, spi-4 phase 2 (pos-phy level 4), hypertransport ? technology, and sfi-4 support for high-speed external memory, including ddr and ddr2 sdram, rldram ii, qdrii sram, and sdr sdram support for multiple intellectual property megafunctions from altera megacore ? functions, and altera megafunction partners program (ampp sm ) megafunctions packaging pin-compatible with stratix ii fpga prototypes up to 951 user i/o pins available available in wire bond an d flip-chip space-saving fineline bga packages ( table 1?3 ).
altera corporation 1?3 september 2008 preliminary feature overview the hardcopy ii device family consists of five devices. table 1?1 summarizes the features availabl e in the hardcopy ii devices. table 1?1. hardcopy ii device family features feature hc210w (1) hc210 hc220 HC230 hc240 asic equivalent gates (2) 1,000,000 1,000,000 1,900,000 2,900,000 3,600,000 m4k ram blocks (4 kbits plus parity) 190 190 408 614 768 (3) m-ram blocks (512 kbits plus parity) 00269 total ram bits (including parity bits) 875,520 875,520 3,059,712 6,368,256 8,847,360 enhanced plls 2 2 2 4 4 fast plls 2 2 2 4 8 maximum user i/o pins (4) , (5) 308 334 494 698 951 notes to ta b l e 1 ? 1 : (1) hc210w devices are in a wire bond package. all other hardcopy ii devices and stra tix ii fpgas use a flip-chip package. devices in a wire bond package offer different performance and signal integrity characteristics compared to devices in a flip-chip package. (2) this is the number of asic equivalent gates available in the hardcopy ii base array, sh ared between both adaptive logic module (alm) logic and dsp functions from a strati x ii fpga prototype. each stratix ii adaptive logic module (alm) is equal to approximately 30 asic equivale nt gates. the number of asic equivalent gates usable is bounded by the number of alms in the companion stratix ii fpga device. (3) total number of usable m4k blocks is 768, which al lows migration compatibility when prototyping with an ep2s180 device. this may be different from the quartu s ii software total physical m4k count of the hc240. (4) the i/o pin counts include the dedicated clk input pins, which can be used for clock signals or data inputs. (5) the quartus ii i/o pin counts include an additional pin ( pllena ), which is not available as a general-purpose i/o pin. the pllena pin can only be used to enable the plls.
1?4 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 migration and packaging overview hardcopy ii devices offer pin-to-pi n compatibility to the stratix ii prototype, which makes them drop-i n replacements for the fpgas. therefore, the same system board and software developed for prototyping and field trials can be retained, enabling the fastest time-to-market for high-volume prod uction. when migrating a specific stratix ii fpga to a hardcopy ii device, there are a number of fpga prototype choices, as shown in table 1?2 . depending on the design resource needs, designers can choose an appropriate hardcopy ii device. table 1?2. stratix ii fpga to hardcopy ii migration paths hardcopy ii device package stratix ii device ep2s30 ep2s60 ep2s90 ep2s130 ep2s180 hc210w 484-pin fineline bga (1) vv v (2) hc210 484-pin fineline bga vv v (2) hc220 672-pin fineline bga v hc220 780-pin fineline bga v v (2) HC230 1,020-pin fineline bga vv v (2) hc240 1,020-pin fineline bga v hc240 1,508-pin fineline bga v notes to ta b l e 1 ? 2 : (1) the hc210w device uses a wire bond package while the stratix ii fpga prototype device uses a pin-compatible flip-chip package. (2) depending on design specific resour ce utilization, an opport unistic migration path may exist between this device pair. be sure to confirm your design is a potential can didate for such a path by fitting with the quartus ii software and consulting an altera applications engineer.
altera corporation 1?5 september 2008 preliminary document revision history hardcopy ii devices are availabl e in the packages shown in table 1?3 . document revision history table 1?4 shows the revision history for this chapter. table 1?3. hardcopy ii package options and i/o pin counts notes (1) , (2) package 484-pin fineline bga (3) 484-pin fineline bga (3) 672-pin fineline bga 780-pin fineline bga 1,020-pin fineline bga 1,508-pin fineline bga type wire bond flip-chip flip-chip fl ip-chip flip-chip flip-chip dimension pitch (mm) 1.00 1.00 1.00 1.00 1.00 1.00 area (mm 2 ) 529 529 729 841 1,089 1,600 length width (mm mm) 23 23 23 23 27 27 29 29 33 33 40 40 device maximum user i/o pins hc210w 308 hc210 334 hc220 492 494 HC230 698 hc240 742 951 notes to ta b l e 1 ? 3 : (1) the quartus ii i/o pin counts include an additional pin ( pllena ) which is not available as a general-purpose i/o pin. the pllena pin can only be used to enable the plls. (2) the i/o pin counts include the dedicated clk input pins, which can be used for clock signals or data inputs. (3) the ep2s90 fpga prototype uses a 484-pin hybrid fi neline bga package. for more information, refer to the stratix ii device handbook . table 1?4. document revision history (part 1 of 2) date and document version changes made summary of changes september 2008, v2.6 updated chapter number and metadata. ? june 2007, v2.5 minor text edits. ?
1?6 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 december 2006 v2.4 minor updates for the quartus ii software version 6.1.0 merged table 1-3 and table 1-4 added revision history a minor update to the chapter, due to changes in the quartus ii software version 6.1 release. merged table 1-3 and table 1-4. march 2006, v2.3 updated table 1-1 and table 1-3. minor edits and clarifications throughout. october 2005, v2.2. updated graphics july 2005, v2.2. updated graphics may 2005, v2.0 updated table 1?1. updated migration process time. updated ?features? section. january 2005 v1.0 added document to the hardcopy series handbook. table 1?4. document revision history (part 2 of 2) date and document version changes made summary of changes
altera corporation 2?1 september 2008 preliminary 2. description, architecture, and features introduction altera ? hardcopy ? ii devices feature an architecture that provides high-density, high-performance, and low-power consumption suitable for a variety of applications. hardcopy ii devices are low-cost structured asics with pin-outs, densities, an d architecture that complement stratix ? ii fpgas. hardcopy ii devices make optimal use of die area and core resources while offering features that are functionally equivalent to the stratix ii fpga. the combination of stratix ii fpgas for in-system prototype and design verification, ha rdcopy ii devices for high-volume production, and the quartus ? ii design software, provide a complete, seamless path from prototype to volume production. table 2?1 provides an overview of the hardcopy ii device features. table 2?1. hardcopy ii family overview (part 1 of 2) feature hc210w (1) hc210 hc220 HC230 hc240 asic gates (2) 1,000,000 1,000,000 1,900,000 2,900,000 3,600,000 m4k ram blocks (4k bits plus parity) 190 190 408 614 768 (3) m-ram blocks (512k bits plus parity) 00 2 6 9 total ram bits (including parity bits) 875,520 875,520 3,059,712 6,368,256 8,847,360 enhanced plls 2 2 2 4 4 fast plls 2 2 2 4 8 package (maximum user i/o pins) (4) , (5) 484-pin fineline bga (308) 484-pin fineline bga (334) 672-pin fineline bga (492) 780-pin fineline bga (494) 1,020-pin fineline bga (698) 1,020-pin fineline bga (742) 1,508-pin fineline bga (951) h51016-2.5
2?2 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 functional description the hardcopy ii device family provides greater flexibility to design with fpga prototypes before moving to structured asics for production. before seamlessly migrating to the hardcopy ii structured asic, designers can prototype and test their design functionality using a stratix ii fpga. there are multiple options for the prototype fpga, allowing designers to choose the right hardcopy ii device for volume production and maximum cost savings. the quartus ii design software includes features such as the device resource guide, to help select the optimal hardcopy ii device based on the design requirements. f for more information on the device resource guide, refer to the quartus ii support fo r hardcopy ii devices chapter in the hardcopy series handbook . hardcopy ii devices require minimal involvement from the designer in the device migration process. addition ally, unlike asics, the designer is not required to generate test benches, test vectors, or timing and functional simulations since prototyp ing is performed using an fpga. hardcopy ii devices consist of base arrays that are common to all designs for a particular device density, with design-specific customization done using two metal layers. the reprogrammable fpga logic, routing, memory, and fpga configuration-related logic are stripped from hardcopy ii devices. removing all programmable and configuration resources and replacing them with direct metal connections results in considerable die size reduction and cost savings. a fine-grain architecture consisting of an array of hcells extends the die reduction and cost fpga prototype options ep2s30 ep2s60 ep2s90 ep2s30 ep2s60 ep2s90 ep2s60 ep2s90 ep2s130 ep2s90 ep2s130 ep2s180 ep2s180 notes to ta b l e 2 ? 1 : (1) hc210w devices use a wire bond package. all other hardcopy ii devices and stra tix ii fpgas use a flip-chip package. devices in a wire bond package offer different performance and signal integrity characteristics compared to devices in a flip-chip package. (2) this is the number of asic gates available in the hardco py ii base array for both logi c and dsp functions that can be implemented in a stratix ii fpga prototype. (3) total number of usable m4k blocks is 768, which al lows migration compatibility when prototyping with an ep2s180 device. this may be different from the quartu s ii software total physical m4k count of the hc240. (4) the i/o pin counts include the dedicated clock input pi ns, which can be used for clock signals or data inputs. (5) the quartus ii i/o pin counts include an additional pin ( pllena ), which is not available as a general-purpose i/o pin. the pllena pin can only be used to enable the plls. table 2?1. hardcopy ii family overview (part 2 of 2) feature hc210w (1) hc210 hc220 HC230 hc240
altera corporation 2?3 september 2008 preliminary functional description savings, which results in low-cost structured asics with high-performance and low-power su itable for a wide variety of applications. the sram configuration cells of the stratix ii fpgas are replaced in hardcopy ii devices with metal connec tions, which defi ne the function of logic, memory, phase- locked loop (pll), and i/o elements (ioes) in the device. these resources are interconnected using metallization layers. once a hardcopy ii device is manu factured, the functionality of the device is fixed. hardcopy ii devices are manufactured using the same 90-nm process technology and operate using the same core voltage (1.2 v) as stratix ii fpgas. additionally, almost all architectural features in hardcopy ii devices are functionally equivalent to features found in the stratix ii fpga architecture. hardcopy ii devi ces feature hcells, memory blocks, plls, and ioes ( figure 2?1 ). figure 2?1. example block diagram of HC230 device note (1) note to figure 2?1 : (1) figure 2?1 shows a graphical representation of the device floor plan. a detailed floor plan is available in the quartus ii software. ioe fast pll enhanced pll fast pll ioe ioe ioes m-ram block ioe ioe ioe ioe ioe ioe ioe ioe ioe ioe ioe array of hcells array of hcells array of hcells array of hcells array of hcells array of hcells m4k ram blocks m4k ram blocks
2?4 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 hardcopy ii and stratix ii similarities and differences hardcopy ii devices preserve the fu nctionality of stratix ii fpgas. implementation of these architectural features in hardcopy ii structured asics matches stratix ii fpga implem entation, with a few exceptions. table 2?2 shows a qualitative comparison of hardcopy ii device feature implementation versus stratix ii fpga feature implementation. other sections within this chapter provide de tails on similarities and differences of a particular hardcopy ii feature. the major similarities and differences between stratix ii fpgas and hardcopy ii devices are highlighted below: hardcopy ii may result in a power reduction of up to 50% than an equivalent stratix ii fpgas operat ing at the same frequency. power consumption is design dependent and is a direct result of design performance and resource utilization. hardcopy ii devices offer up to 100% performance improvement when compared to stratix ii fpga prototypes. the performance improvement is achieved by effi cient use of logic blocks, metal interconnect optimization, die size reduction, and customized signal buffering. logic blocks, known as hcells, are the basic building block of the core logic in hardcopy ii devices an d replace stratix ii adaptive logic modules (alms). hcells implement logic and dsp functions. dsp block functions are implemen ted using hcells, instead of dedicated dsp blocks. m4k and m-ram memory blocks can implement various types of memory (the same as stratix ii fpgas), with or without parity, including true dual-port, simple dual-port, and single-port ram, rom, and first-in first-out (fifo) buffers. table 2?2. hardcopy ii device vs. st ratix ii fpga feature implementation feature equivalent different logic blocks v dsp blocks v memory v clock networks v plls v i/o features v configuration (1) v note to ta b l e 2 ? 2 : (1) hardcopy ii structured asics do not n eed to be configured upon power-up.
altera corporation 2?5 september 2008 preliminary hardcopy ii and stratix ii similarities and differences unlike stratix ii fpgas, the hardco py ii m4k block contents cannot be pre-loaded with a memory initialization file ( .mif ) when used as ram. when used as rom, hardcopy ii m4k blocks are initialized to the rom contents. when used as ram, and you select the non-registered output mode, hardcopy ii m4k and m-ram bloc ks power up with outputs unknown. in stratix ii fpgas, m4 k blocks power up with outputs cleared, while m-ram blocks powe r up with outputs unknown. if registered outputs mode is selected, the outputs are cleared on both the m4k and m-ram blocks in hardcopy ii. the memory contents are unknown under both instances. all hardcopy ii clock network features are the same as in stratix ii fpgas. enhanced pll and fast pll implementations in hardcopy ii devices are the same as in stratix ii fpgas. all stratix ii i/o features and supported i/o standards are offered in hardcopy ii devices. the joint test action group (jtag) boundary scan order and length in hardcopy ii devices is differen t than that of the stratix ii fpga. use a hardcopy ii boundary-scan description language (bsdl) file that describes the re-ordered an d shortened boundary scan chain. unlike stratix ii devices, hardcopy ii devices are customized using two metal layers. therefore, config uration circuitry is not required. fpga configuration emulation an d other configuration modes, including remote system upgrades and design security using configuration bitstream encryption, are not supported in hardcopy ii devices. even though configuration is not required, the crc_error pin function is supported by the hardco py ii using quartus ii software version 6.0 and above. there is no need to recompile the stratix ii design to eliminate this feature. 1 only supplementary informatio n to highlight hardcopy ii similarities and differences comp ared to the stratix ii fpga architecture and functionality is provided in this chapter. for more information on similarities and differences of available resources of the hardcopy ii, refer to the migrating stratix ii device resources to hardcopy ii devices chapter of this handbook. in addition, the stratix ii device handbook has detailed explanations of architectural fe atures and functions that are similar to the hardcopy ii devices.
2?6 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 hcells hardcopy ii devices are built using an array of fine-grained architecture blocks called hcells. hcells are a collection of logic transistors based on 1.2 v, 90 nm process technology, similar to stratix ii devices. the construction of logic usin g hcells allows flexible functionality such that when hcells are combined, all viable logic combinations of stratix ii functionality are replicat ed. these hcells constitu te the array of hcells area in figure 2?1 . only hcells needed to implement the customer design are assembled together, whic h optimizes hcell utilization. the unused area of the hcell logic fabric is powered down, resulting in significant power savings compared with the stratix ii fpga prototype. the quartus ii software uses the li brary of pre-characterized hcell macros to place stratix ii alm an d dsp configurations into the hardcopy ii hcell-based logic fabr ic. an hcell macro defines how a group of hcells are connected together within the array. hcell macros can construct all combinations of combinational logic, adder, and register functions that can be implemented by a stratix ii alm. hcells not used for alm configurations can be used to implement dsp block functions. based on design requirements, the quartus ii software will chose the appropriate hcell macros to implemen t the design functionality. for example, stratix ii alms offer flex ible look-up table (lut) blocks, registers, arithmetic blocks, and lab-wide control signals. in hardcopy ii devices, if your design requires these architectural elements, the quartus ii synthesis tool will map the design to the appropriate hcells, resulting in improved design performance compared to the stratix ii fpga prototype. stratix ii fpgas have dedicated ds p blocks to implement various dsp functions. stratix ii dsp blocks co nsist of a multiplier block, an adder/subtractor/accumulator block, a summation block, input and output interfaces, and input and ou tput registers. in hardcopy ii devices, hcell macros implement stra tix ii dsp block functionality with area efficiency and performance on pa r with the dedicated dsp blocks in stratix ii fpgas. there are eight hcell macros which implement the eight supported modes of operation for the stratix ii dsp block: 9 9 multiplier 9 9 two-multiplier adder (9 9 complex multiply) 9 9 four-multiplier adder 18 18 multiplier 18 18 two-multiplier adder (18 18 complex multiply) 18 18 four-multiplier adder 52-bit (18 18) multiplier-accumulator 36 36 multiplier
altera corporation 2?7 september 2008 preliminary hcells only hcells that are re quired to implement the design?s dsp functions are enabled. hcells not needed for dsp functions can be used for alm configurations, which results in efficient logic usage. in addition to area management, the placement of these hcell macros allows for optimized routing and performance. an example of efficient logic area usage can be seen when comparing the 18 18 multiplier implementation in stratix ii fpgas using the dedicated dsp block versus the implementati on in hardcopy ii devices using hcells. if the stratix ii dsp function only calls for one 18 18 multiplier, the other three 18 18 multipliers and the dsp block?s adder output block are not used ( figure 2?2 ). in hardcopy ii devices, the hcell-based logic fabric that is not used for dsp func tions can be used to implement other combinational logic, adder, and register functions. figure 2?2. stratix ii dsp block versus hardcopy ii hcell 18 18-bit mul tiplier implementation hardcopy ii devices support all stratix ii dsp configurations (9 9, 18 18, and 36 36 multipliers) and all stratix ii dsp block features, such as dynamic sign controls, dynamic addition/subtraction, saturation, rounding, and dynamic input shift registers, except for dynamic mode switching. input registers 1 8 1 8 multiplier 18 18 multiplier 18 18 multiplier 18 18 multiplier input registers output registers output registers adder/ subtractor/ accumulator block input registers 1 8 1 8 multiplier output registers used portions of the block unused portions of the block stratix ii dsp block hardcopy ii hcell-based logic fabric these elements are implemented using hcell macros. unused logic area can be used to perform other logic functions.
2?8 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 dynamic mode switching allows the designer to set up each stratix ii dsp block to dynamically switch between the following three modes: up to four 18-bit independent multipliers up to two 8-bit multiplier-accumulators one 36-bit multiplier each half of a stratix ii dsp block has separate mode control signals. since dsp block functions are implem ented in hardcopy ii devices using hcells, hardcopy ii devices do not support dynamic mode switching. if this feature is used, the quartus ii software flags the dsp implementation and does not allow you to migrate the design. the fitter reports that all hardcopy ii devices are not compatible with the design. to migrate your stratix ii design to a hardcopy ii companion device, disable dynamic switching in the dsp blocks. f for more information on the stratix ii dsp operational modes, refer to the stratix ii device handbook . embedded memory hardcopy ii memory blocks can im plement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port ram, rom, and fifo buffers. hardcopy ii devices support the same memory functions and features as stratix ii fpgas. functionally, the memory in both devices are id entical. however, the number of available memory blocks differs based on density ( table 2?3 ). since device functionality is fixed in hardcopy ii devices, m4k block contents cannot be preloaded or in itialized with a mif when they are configured as ram. when the m4k bl ocks are used as rom, they will initialize to the design?s rom contents. when using the non-registered outputs mode for the hardcopy ii m4k memory block, the outputs power up uninitialized. when using the registered outputs mode for the hardcopy ii m4k memory blocks, the table 2?3. hardcopy ii embedded memory resources feature hc210w hc210 hc220 HC230 hc240 m4k ram blocks (4 kbits) 190 190 408 614 768 m-ram blocks (512 kbits) 0 0 2 6 9 total ram bits (bits) 875,520 875,520 3,059,712 6,368,256 8,847,360
altera corporation 2?9 september 2008 preliminary plls and clock networks outputs are cleared on power up. the designer needs to take these into consideration when designing logic that might evaluate the initial power-up values of the memory block. hardcopy ii embedded memory consists of m4k and m-ram memory blocks and have a one-to-one mapping from stratix ii m4k and m-ram resources. table 2?4 shows the size and features of the different ram blocks. f for more information on the stratix ii memory block features, refer to the stratix ii device handbook . plls and clock networks both hardcopy ii enhanced and fast plls are feature rich, supporting advanced capabilities such as clock switchover, reconfigurable phase shift, pll reconfiguration, and reconf igurable bandwidth. plls are used for general-purpose clock manage ment, supporting multiplication, division, phase shifting, and progra mmable duty cycle. in addition, enhanced plls support external clock feedback mode, spread-spectrum clocking, and counter cascading. fast plls offer high speed outputs to manage the high-speed differential i/o interfaces. 1 all stratix ii pll features are supported by hardcopy ii plls. similar to stratix ii fpgas, hardcopy ii devices also support a power-down mode where unused clock networks can be disabled. hardcopy ii and stratix ii clock control blocks support dynamic selection of the input clock from up to four possible sources, giving the designer the flexibility to choose from multiple (up to four) clock sources.
2?10 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 table 2?4. hardcopy ii embedded memory features (part 1 of 2) notes (1) , (2) , (3) feature m4k blocks m-ram blocks maximum performance (1) , (4) 350 mhz 350 mhz total ram bits (including parity bits) 4,608 589,824 configurations 4k 1 2k 2 1k 4 512 8 512 9 256 16 256 18 128 32 128 36 64k 8 64k 9 32k 16 32k 18 16k 32 16k 36 8k 64 8k 72 4k 128 4k 144 parity bits vv byte enable vv pack mode vv address clock enable vv single-port memory vv simple dual-port memory vv true dual-port memory vv embedded shift register v rom v fifo buffer vv simple dual-port mixed width support vv true dual-port mixed width support vv memory initialization file (. mif ) not supported, except in rom mode not supported mixed-clock mode vv power-up condition (2) outputs unknown outputs unknown register clears (3) output registers only output registers only same-port read-during-write new data available at positive clock edge new data available at positive clock edge mixed-port read-during-write outputs set to unknown or old data unknown output
altera corporation 2?11 september 2008 preliminary plls and clock networks enhanced and fast plls the number of plls availabl e differs based on density ( table 2?5 ). the target hardcopy ii device may not support the same number of enhanced plls as the prototyping stratix ii fpga. however, since hardcopy ii enhanced plls and fast plls offer a similar feature set ( table 2?7 on page 2?13 ), a fast pll could be used in place of an enhanced pll. the type of pll used in the design should be chosen using the quartus ii software to accommodate the resources available in the hardcopy ii device. table 2?6 shows which plls are available in each device density. figure 2?3 shows the location of each pl l. during the prototyping stage using the fpga, you must select the appropriate number of enhanced and fast plls that will be used in your hardcopy ii device. use table 2?6 to ensure that the fpga prototyping design uses the same pll resources available in the hardcopy ii device. note to ta b l e 2 ? 4 : (1) maximum performance information is pr eliminary until device characterization. (2) the memory cells power up randomly, so reads before w rites are not valid. make sure you write to the memory location before you read it. (3) even though the output register is cleared, the memory cells power up randomly. so reads before write are not valid. make sure you write to the memo ry location first before reading it. (4) violating the setup or hold time requirements on the address registers could corrupt the memory contents. this applies to both read and write operations. table 2?4. hardcopy ii embedded memory features (part 2 of 2) notes (1) , (2) , (3) feature m4k blocks m-ram blocks table 2?5. hardcopy ii plls feature hc210w hc210 hc220 HC230 hc240 enhanced plls 22244 fast plls 22248 table 2?6. hardcopy ii plls available (part 1 of 2) note (1) device fast plls enhanced plls 123478910561112 hc210w vv vv hc210 vv vv
2?12 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 figure 2?3. hardcopy ii pll locations notes (1) , (2) notes to figure 2?3 : (1) the plls may be located in the perip hery or in the core of the device. (2) this is the die-level top view of the device and is only a graphical representation of the pll locations. hc220 vv vv HC230 vv vv vvvv hc240 vvvvvvvvvvvv note to ta b l e 2 ? 6 : (1) pll performance in the hc210w device ma y differ from the stratix ii fpga prototype. table 2?6. hardcopy ii plls available (part 2 of 2) note (1) device fast plls enhanced plls 123478910561112 fpll8clk clk[3..0] 1 2 8 6 12 clk[7..4] plls
altera corporation 2?13 september 2008 preliminary plls and clock networks pll functionality in hardcopy ii devices remains the same as in stratix ii fpga plls. therefore, the hardcopy ii plls support pll reconfiguration (the pll can be dyna mically configured in user mode). hardcopy ii enhanced and fast plls support a one-to-one mapping from stratix ii pll resources. table 2?7 shows the features of the different plls. for more information on the stratix ii pll features, refer to the stratix ii device handbook . table 2?7. hardcopy ii pll features feature enhanced pll fast pll clock multiplication and division m/(n post-scale counter) (1) m/(n post-scale counter) (2) phase shift down to 125-ps increments (3) down to 125-ps increments (3) clock switchover vv (4) pll reconfiguration vv reconfigurable bandwidth vv spread-spectrum clocking v programmable duty cycle vv number of clock outputs per pll (5) 64 number of dedicated external clock outputs per pll three differential or six singled- ended (6) number of feedback clock inputs per pll 1 (7) notes to ta b l e 2 ? 7 : (1) for enhanced plls, m and n range from 1 to 512 and post-scale counters range from 1 to 512 with 50% duty cycle. for non-50% duty-cycle clock outputs, post -scale counters range from 1 to 256. (2) for fast plls, n can range from 1 to 4. the post-scale and m counters range from 1 to 32. for non-50% duty-cycle clock outputs, post-scale counters range from 1 to 16. (3) the smallest phase shift is determined by the voltage controlled osc illator (vco) period divided by eight. the supported phase shift range is from 125 to 250 ps. ha rdcopy ii devices can shift all output frequencies in increments of at least 45 . smaller degree increments are possible depending on the frequency and divide parameters. for non-50% duty cycle clock outputs post-scale counters range from 1 to 256. (4) hardcopy ii fast plls only support manual clock switchover. (5) the clock outputs can be driven to internal clock networks or to a pin. (6) the pll clock outputs of the fast plls can drive to any i/o pin to be used as an external clock output. for high-speed differential i/o pins, the device uses a da ta channel to generate the transmitter output clock ( txclkout ) . (7) if the design uses external feedback in put pins, you will lose one (or two, if f bin is differential) dedicated external clock output pin.
2?14 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 clock networks there are 16 clock pins ( clk[15..0] ) in hardcopy ii devices that can drive either the global- or regional-clock networks. the clk pins can drive clock ports or data inputs. hardcopy ii devices provide 16 dedi cated global-clock networks and 32 regional-clock networks ; the same as in stratix ii fpgas. these clocks are organized to provide 24 unique clock sources per device quadrant with low skew and delay. this clocki ng scheme provides up to 48 unique clock domains within the entire hardcopy ii device. table 2?8 lists the clock resources and features available in hardcopy ii devices. hardcopy ii devices also support the sa me features as the stratix ii clock control block, which is available fo r each global- and regional-clock network. the control bl ock has two functions: clock source selection (dynamic selection for global clocks): you user can either dynamically select between two pll outputs, between two clock pins ( clkp or clkn ), or a combination of the clock pins or pll outputs. clock power-down (dynamic clock enable or disable): in hardcopy ii devices, you can dyna mically turn the clock off or on in user-mode. i/o structure and features the structure and features of the hardcopy ii ioe remains the same as in stratix ii. any feature implemented in stratix ii ioes can be migrated to hardcopy ii ioes. table 2?8. clock network resources and featur es available in hardcopy ii devices resources and features availability number of global clock networks 16 number of regional clock networks 32 global clock input sources clock i nput pins, pll outputs, logic array regional clock input sources clock i nput pins, pll outputs, logic array number of unique clock sources in a quadrant 24 (16 global clocks and 8 regional clocks) number of unique clock sources in the entire de vice 48 (16 global clocks and 32 regional clocks) power-down mode global- and regional-clock networks, dual-regional-clock region clocking regions for high fan-out applications quadr ant region, dual-regional, entire device via global- or regional-clock networks
altera corporation 2?15 september 2008 preliminary i/o structure and features the ioe feature set in hardcopy ii devices can be classified in one of three categories: general purpose ioes?the most commonly used i/o type in designs. memory interface ioes?include s features to interface with common external memory standards. high-speed ioes?supports high-s peed data transmission and reception. all i/o pins in stratix ii fpgas su pport general-purpose i/o standards, which includes the lvttl and lvcm os i/o standards. in stratix ii fpgas, the pci clamping diode and me mory interfaces are supported on the top and bottom i/o pins, while hi gh-speed interfaces are supported on the left and right side i/o pins of the device. the new general purpose ioes in hardcopy ii devices are a cost saving and area efficient advantage. the complex memory interface and the high-speed ioe circuitry is removed to save die area while still offering the more commonly-used features. the memory interface ioe supports all the features availabl e in the general purpose ioe. the high-speed ioe also supports all the same features and i/o standards as the general purpose ioe, except for the pci cl amping diode (supported on the bottom general purpose ioes in hc210 and hc220 devices). in order to increase the i/o area effi ciency of hardcopy ii devices, the features available on any given ioe depends on the location. table 2?9 shows which i/o standards are supported by the different ioe types. table 2?9. hardcopy ii suppor ted i/o standards (part 1 of 3) i/o standard type v ccio level (v) memory interface ioes general purpose ioes high-speed ioes input output 3.3-v lvttl/ lv c m o s single-ended 3.3/2.5 3.3 vvv 2.5-v lvttl/ lv c m o s single-ended 3.3/2.5 2.5 vvv 1.8-v lvttl/ lv c m o s single-ended 1.8/1.5 1.8 vvv 1.5-v lvcmos single-ended 1.8/1.5 1.5 vvv sstl-2 class i voltage referenced 2.5 2.5 v
2?16 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 sstl-2 class ii voltage referenced 2.5 2.5 v sstl-18 class i voltage referenced 1.8 1.8 v sstl-18 class ii voltage referenced 1.8 1.8 v 1.8-v hstl class i voltage referenced 1.8 1.8 v 1.8-v hstl class ii voltage referenced 1.8 1.8 v 1.5-v hstl class i voltage referenced 1.5 1.5 v 1.5-v hstl class ii voltage referenced 1.5 1.5 v pci/pci-x single-ended 3.3 3.3 v (2) v (2) differential sstl-2 class i and ii input pseudo differential (1) 3.3/2.5/ 1.8/1.5 (3) differential sstl-2 class i and ii output pseudo differential (1) 2.5 (3) differential sstl-18 class i and ii input pseudo differential (1) 3.3/2.5/ 1.8/1.5 (3) differential sstl-18 class i and ii output pseudo differential (1) 1.8 (3) 1.8-v differential hstl class i and ii input pseudo differential (1) 3.3/2.5/ 1.8/1.5 (3) 1.8-v differential hstl class i and ii output pseudo differential (1) 1.8 (3) 1.5-v differential hstl class i and ii input pseudo differential (1) 3.3/2.5/ 1.8/1.5 (3) 1.5-v differential hstl class i and ii output pseudo differential (1) 1.5 (3) lvds differential 2.5 2.5 (5) (4) , (6) v hypertransport? technology differential 2.5 2.5 (5) (4) , (6) v table 2?9. hardcopy ii suppor ted i/o standards (part 2 of 3) i/o standard type v ccio level (v) memory interface ioes general purpose ioes high-speed ioes input output
altera corporation 2?17 september 2008 preliminary i/o structure and features the three types of ioes are located in different areas of the device and are described in the following sections. hardcopy ii devices have eight i/o banks, just as in stratix ii fpgas. figures 2?4 through 2?6 show which i/o type each bank supports. lvpecl differential 3.3/2.5/ 1.8/1.5 (8) (8) (8) notes to ta b l e 2 ? 9 : (1) pseudo-differential hstl and sstl inputs only use the positive-polarity input in the speed path. the negative input is not connected internally. pseudo-differential hstl and sstl outputs use two single-ended outputs with the second output programmed as inverted. this is similar to a stratix ii device implementation. (2) the pci clamping diode is only supported on the i/o pins on the top and bo ttom sides of the device. (3) this i/o standard is on ly supported on the dqs, clk and pll_fb input pins or on the pll_out output pins. (4) this i/o standard is only supported on the bottom clk and pll_fb input pins or on the bottom pll_out output pins. (5) this i/o standard is only supported on the clk and pll_fb input pins or on the pll_out output pins. (6) also supported on clk9 and clk11 pins. (7) this i/o standard is only supported on clk and pll_fb input pins. (8) lvpecl input i/o standard is supported on the top and bottom clk and pll_fb input pins. lvpecl output i/o standard is supported on the top and bottom pll_out output pins. lvpecl support is similar to stratix ii devices. table 2?9. hardcopy ii suppor ted i/o standards (part 3 of 3) i/o standard type v ccio level (v) memory interface ioes general purpose ioes high-speed ioes input output
2?18 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 figure 2?4. i/o type support in hc210 and hc220 devices notes (1) , (2) bank 4 memory interface ioes pll 5 bank 9 bank 7 general purpose ioes bank 8 general purpose ioes pll 6 bank 10 i/o banks 3 & 4 support 3.3-v, 2.5-v, 1. 8 -v lvttl/ lvcmos, 1.5-v lvcmos, sstl-2, sstl-1 8 , 1. 8 -v hstl, 1.5-v hstl & pci/pci-x i/o standards. i/o banks 7 & 8 support 3.3-v, 2.5-v, 1. 8 -v lvttl/ lvcmos, 1.5-v lvcmos & pci/pci-x i/o standards. bank 3 memory interface ioes bank 2 high-speed ioes bank 1 high-speed ioes bank 5 general-purpose ioe s bank 6 general-purpose ioe s pll 1 pll 2 i/o banks 1 & 2 support 3.3-, 2.5- & 1. 8 -v lvttl/lvcmos, 1.5-v lvcmos, lvds & hypertransport technology clk, pll_fb input pins & pll_out output pins support differential sstl, differential hstl, lvds & hypertransport technology. clk & pll_fb pins support lvpecl. dqs input pins support differential sstl and differential hstl i/o standards. clk, pll_fb input pins & pll_out output pins support differential sstl, differential hstl, lvds & hypertransport technology. clk & pll_fb pins support lvpecl. i/o banks 5 & 6 support 3.3-, 2.5- & 1. 8 -v lvttl/lvcmos &1.5-v lvcmos
altera corporation 2?19 september 2008 preliminary i/o structure and features figure 2?5. i/o type support in HC230 devices notes (1) , (2) bank 4 memory interface ioes pll 5 pll 11 bank 11 bank 9 bank 7 memory interface ioes bank 8 memory interface ioes i/o banks 3 & 4 support 3.3-v, 2.5-v, 1. 8 -v lvttl/ lvcmos, 1.5-v lvcmos, sstl-2, sstl-1 8 , 1. 8 -v hstl, 1.5-v hstl & pci/pci-x i/o standards. i/o banks 7 & 8 support 3.3-v, 2.5-v, 1. 8 -v lvttl/ lvcmos, 1.5-v lvcmos & pci/pci-x i/o standards. bank 3 memory interface ioes pll 6 pll 12 bank 2 high-speed ioes bank 1 high-speed ioes bank 5 general-purpose ioe s bank 6 general-purpose ioe s pll 1 pll 2 i/o banks 5 & 6 support 3.3-, 2.5- & 1. 8 -v lvttl/lvcmos &1.5-v lvcmos i/o banks 1 & 2 support 3.3-, 2.5- & 1. 8 -v lvttl/lvcmos, 1.5-v lvcmos, lvds & hypertransport technology bank 12 bank 10 pll 7 pll 8 clk, pll_fb input pins & pll_out output pins support differential sstl, differential hstl, lvds & hypertransport technology. clk & pll_fb pins support lvpecl. dqs input pins support differential sstl and differential hstl i/o standards. clk, pll_fb input pins, sstl-2, sstl-1 8 , 1. 8 -v hstl, 1.5-v hst, & pll_out output pins support differential sstl, differential hstl, lvds & hypertransport technology. clk & pll_fb pins support lvpecl. dqs input pins support differential sstl and differential hstl i/o standards.
2?20 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 figure 2?6. i/o type support in hc240 devices notes (1) , (2) notes to figures 2?4 through 2?6 : (1) in addition to supporting external memory interfaces, memory interface ioes have the same features as general purpose ioes. in addition to supporting high-speed i/o interfaces, high-speed ioes have the same features as general purpose ioes, except for the pci clam ping diode and lvpecl clock input support. (2) this is a top view of the silicon die which corresponds to a reverse view for flip-chip packages. it is a graphical representation only. 1 when planning i/o placement for designs targeting hardcopy ii devices, care should be taken to ensure the same i/o standards are supported in the same hardcopy ii i/o banks as in the stratix ii i/o banks. general purpose ioe the general purpose ioes in hc210 and hc220 devices are located on the right side and at the bottom of the device. the general purpose ioes in HC230 devices are located on the right side of the device. (directions are based on a top view of the silicon die.) hc240 devices do not have general purpose ioes. the general purpose ioe functionality is supported in the memory interface ioes for these de vices. the high-speed ioes also bank 4 memory interface ioes bank 7 memory interface ioes bank 8 memory interface ioes i/o banks 3 & 4 support 3.3-v, 2.5-v, 1. 8 -v lvttl/ lvcmos, 1.5-v lvcmos, sstl-2, sstl-1 8 , 1. 8 -v hstl, 1.5-v hstl & pci/pci-x i/o standards. i/o banks 7 & 8 support 3.3-v, 2.5-v, 1. 8 -v lvttl/ lvcmos, 1.5-v lvcmos & pci/pci-x i/o standards. bank 3 memory interface ioes bank 2 high-speed ioes bank 1 high-speed ioes bank 5 high-speed ioe s bank 6 high-speed ioe s pll 1 pll 2 pll 4 pll 3 i/o banks 5 & 6 support 3.3-, 2.5- & 1. 8 -v lvttl/lvcmos, 1.5-v lvcmos, lvds & hypertransport technology i/o banks 1 & 2 support 3.3-, 2.5- & 1. 8 -v lvttl/lvcmos, 1.5-v lvcmos, lvds & hypertransport technology clk, pll_fb input pins & pll_out output pins support differential sstl, differential hstl, lvds & hypertransport technology. clk & pll_fb pins support lvpecl. dqs input pins support differential sstl and differential hstl i/o standards. clk, pll_fb input pins sstl-2, sstl-1 8 , 1. 8 -v hstl, 1.5-v hst, & pll_out output pins support differential sstl, differential hstl, lvds & hypertransport technology. clk & pll_fb pins support lvpecl. dqs input pins support differential sstl and differential hstl i/o standards. pll 5 pll 11 bank 11 bank 9 pll 6 pll 12 bank 12 bank 10 pll 10 pll 9 pll 7 pll 8
altera corporation 2?21 september 2008 preliminary i/o structure and features provide the same features as the general purpose ioes except for the pci clamping diode. in stratix ii fpgas, all ioes support the general purpose ioe features except the pci diode, which is only supported on the top and bottom i/o pins. the general purpose ioe has many features, including: dedicated single-ended i/o buffers 3.3-v, 64-bit, 66 mhz pci compliance 3.3-v, 64-bit, 133 mhz pci-x 1.0 compliance jtag boundary-scan test (bst) support on-chip driver series termination (non-calibrated) output drive strength control tri-state buffers bus-hold circuitry programmable pull-up resistors open-drain outputs pci clamping diode (supported on the bottom i/o pins only) double data rate (ddr) registers general purpose ioes support the following i/o standards: 3.3-v lvttl/lvcmos 2.5-v lvttl/lvcmos 1.8-v lvttl/lvcmos 1.5-v lvcmos 3.3-v pci 3.3-v pci-x mode 1 the general purpose clk and pll_fb input pins and the pll_out output pins support the following i/o standards: lvds hypertransport technology lvpecl (on input clocks and pll_out only) the programmable drive strengths available vary depending on the i/o standard being used and are listed in table 2?10 . table 2?10. programmable drive strength support for general-purpose ioes (part 1 of 2) i/o standard programmable drive strength options (ma) 3.3-v lvttl 4, 8, 12 3.3-v lvcmos 4, 8 2.5-v lvttl/lvcmos 4, 8, 12
2?22 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 general purpose ioes support non-cali brated on-chip seri es termination. 50- and 25- on-chip series termination is available for 3.3-v or 2.5-v i/o standards. 50- on-chip series termination is available for 1.8- and 1.5-v i/o standards (pending characterization). memory interface ioe memory interface ioes in hc210 and hc220 devices are located on the top of the device. memory interf ace ioes in HC230 and hc240 devices are located on the top and the bottom of the device. in stratix ii fpgas, the top and bottom ioes support the memory interface ioe features. the memory interface ioe has many features, including: dedicated single-ended i/o buffers 3.3-v, 64-bit, 66 mhz pci compliance 3.3-v, 64-bit, 133 mhz pci-x 1.0 compliance jtag bst support on-chip driver series termination v ref pins output drive strength control tri-state buffers bus-hold circuitry programmable pull-up resistors open-drain outputs pci clamping diode dq and dqs i/o pins double data rate (ddr) registers the following i/o standards are supported when using the memory interface ioes and can be used to in terface to external memory, including ddr and ddr2 sdram, and qdrii, rldram ii, and sdr sram: 3.3-v lvttl/lvcmos 2.5-v lvttl/lvcmos 1.8-v lvttl/lvcmos 1.5-v lvcmos 3.3-v pci 3.3-v pci-x mode 1 1.8 v lvttl/lvcmos 2, 4, 6, 8 1.5 v lvcmos 2, 4 table 2?10. programmable drive strength support for general-purpose ioes (part 2 of 2) i/o standard programmable drive strength options (ma)
altera corporation 2?23 september 2008 preliminary i/o structure and features sstl-2 class i and ii sstl-18 class i and ii 1.8-v hstl class i and ii 1.5-v hstl class i and ii the memory interface dqs, clk , and pll_fb input pins and the pll_out output pins support the following i/o standards: lvttl/lvcmos sstl-2 class i and ii sstl-18 class i and ii 1.8-v hstl class i and ii 1.5-v hstl class i and ii differential sstl-2 class i and ii differential sstl-18 class i and ii 1.8-v differential hstl class i and ii 1.5-v differential hstl class i and ii lvds (not support ed on dqs pins) hypertransport technology (n ot supported on dqs pins) lvpecl on input clocks and pll_out only (not supported on dqs pins) pseudo-differential hstl and sstl inputs are supported on clock and dqs pins, while outputs ar e supported on dedicated pll_out and dqs pins. pseudo-differential hstl and sstl i/o standards use two single-ended outputs with the second output programmed as inverted. pseudo-differential hstl and sstl inputs treat differential inputs as two single-ended hstl and ss tl inputs and only decode one of them. this i/o support is the same as in stratix ii fpgas. the functionality of all dqs circuitry in hardcopy ii devices is the same as in stratix ii fpgas. table 2?11 shows the number of dqs/dq groups supported in each hardcopy ii device density and package. table 2?11. dqs and dq bus mode support (part 1 of 2) device package number of 4 groups number of 8/9 groups number of 16/18 groups number of 32/36 groups hc210w 484-pin fineline bga (wire bond) 42 0 0 hc210 484-pin fineline bga 4 2 0 0 hc220 672-pin fineline bga 9 4 2 0 780-pin fineline bga 9 4 2 0 HC230 1,020-pin fineline bga 36 18 8 4
2?24 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 the programmable drive strengths available vary depending on the i/o standard used. the options are listed in table 2?12 . memory interface ioes support both non-calibrated and calibrated on-chip series termination. 50- and 25- on-chip series termination is available for 3.3-, 2.5-, or 1.8-v i/o standards. 50- on-chip series termination is available for 1.5- or 1.2-v i/o standards (pending characterization). 1 if on-chip series termination is enabled, programmable drive strength support is not available. hc240 1,020-pin fineline bga 36 18 8 4 1,508-pin fineline bga 36 18 8 4 table 2?11. dqs and dq bus mode support (part 2 of 2) device package number of 4 groups number of 8/9 groups number of 16/18 groups number of 32/36 groups table 2?12. programmable drive strength support for memory interface ioes i/o standard programmable drive strength options (ma) 3.3-v lvttl 4, 8, 12, 16, 20, 24 3.3-v lvcmos 4, 8, 12, 16, 20, 24 2.5-v lvttl/lvcmos 4, 8, 12, 16 1.8-v lvttl/lvcmos 2, 4, 6, 8, 10, 12 1.5-v lvcmos 2, 4, 6, 8 sstl-2 class i 8, 12 sstl-2 class ii 16, 20, 24 sstl-18 class i 4, 6, 8, 10, 12 sstl-18 class ii 8, 16, 18, 20 1.8-v hstl class i 4, 6, 8, 10, 12 1.8-v hstl class ii 16, 18, 20 1.5-v hstl class i 4, 6, 8, 10, 12 1.5-v hstl class ii 16, 18, 20
altera corporation 2?25 september 2008 preliminary i/o structure and features high-speed ioe high-speed ioes in hc210, hc220, an d HC230 devices are located on the left side of the device . high-speed ioes in hc240 devices are located on the left and right sides of the device. (directions are based on a top view of the silicon die.) unlike strati x ii left and right side i/o pins, hardcopy ii left and right side i/o pins do not support sstl or hstl i/o standards or the pci clamping diode. in stra tix ii fpgas, the right and left ioes support the high-speed ioe features. the high-speed ioe has many features, including: dedicated single-ended i/o buffers differential i/o buffer jtag bst support on-chip driver series termination (non-calibrated) on-chip termination for di fferential i/o standards output drive strength control tri-state buffers bus-hold circuitry programmable pull-up resistors open-drain outputs transmit serializer receive deserializer dynamic phase alignment (dpa) double data rate (ddr) registers the following i/o standards are supported when using high-speed ioes: 3.3-v lvttl/lvcmos 2.5-v lvttl/lvcmos 1.8-v lvttl/lvcmos 1.5-v lvcmos lvds hypertransport technology
2?26 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 the serdes and dpa circuitry and functionality is the same in hardcopy ii devices as in stratix ii fpgas. hardcopy ii devices support differential i/o standards at rates up to 1 gbps when using dpa, and at rates up to 840 mbps when not using dpa. table 2?13 provides the number of differential channels per hardcopy ii device. hardcopy ii high-speed ioes, which are on the left and/or right sides of the device, support fewer programmable drive strengths than stratix ii side ioes. the programmable drive strengths available vary depending on the i/o standard being used. the options are listed in table 2?14 . high-speed ioes support non-calibrated on-chip series termination and differential termination on the receiver channels. 50- and 25- on-chip series termination is available for 3.3- or 2.5-v i/o standards. 50- on-chip series termination is availa ble for 1.8- and 1.5-v i/o standards (pending characterization). table 2?13. number of differential channels in hardcopy ii devices notes (1) , (2) channel hc210w hc210 hc220 HC230 hc240 484-pin fineline bga (wire- bond) 484-pin fineline bga 672-pin fineline bga 780-pin fineline bga 1,020-pin fineline bga 1,020-pin fineline bga 1,508-pin fineline bga transmitter channels 13 19 29 29 44 88 116 receiver channels 17 21 31 31 46 92 116 notes to ta b l e 2 ? 1 3 : (1) the pin count does not include de dicated pll input and output pins. (2) the total number of receiver channels includes the non- dedicated clock channels that can optionally be used as data channels. table 2?14. programmable drive strength support for high-speed ioes i/o standard programmable drive strength options (ma) 3.3-v lvttl 4, 8, 12 3.3-v lvcmos 4, 8 2.5-v lvttl/lvcmos 4, 8, 12 1.8-v lvttl/lvcmos 2, 4, 6, 8 1.5-v lvcmos 2, 4
altera corporation 2?27 september 2008 preliminary power-up modes power-up modes the functionality of structured asic s is determined before they are produced. therefore, they do not require programmability. hardcopy ii structured asics follow the same principle, enabling traditional asic-like power up. although prototy ping fpgas require configuration upon power up, the hardcopy ii structured asics do not need to be configured. hardcopy ii devices do not support configuration and designers should take this into acco unt in the prototyping-to-production development process. the hardcopy ii device does not require a configuration device, but you must ensure that the n ce pin is low and that the n config and n status pins are high after power up. 1 hardcopy ii devices do not support fpga configuration emulation and other configuration modes, including remote system upgrades and design security using configuration bitstream encryption. hardcopy ii devices support both inst ant on and instant on after 50 ms power-up modes. in the instant on power-up mode, the hardcopy ii device is available for us e shortly after the device powers up to a safe operating voltage. the on-chip power-on reset (por) circuit will reset all registers. the n ce , n config , and n status signals must be at the appropriate logic levels for the conf_done output to be tristated once the por has elapsed. this option is simi lar to an asic?s functionality upon power up and is the most likely scenario in production. in the instant on after 50 ms power-up mode, the hardcopy ii device behaves similarly to the instant on mode, except that there is an additional delay of 50 ms, during which time the device will be held in reset. the conf_done output is pulled low during this time, and then tri-stated after the 50 ms have elapsed. f for more information about whic h power-up modes hardcopy ii devices support, refer to the power-up modes and configuration emulation in hardcopy series devices chapter in the hardcopy series handbook .
2?28 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 document revision history table 2?15 shows the revision history for this chapter. table 2?15.document revision history date and document version changes made summary of changes september 2008, v2.5 updated chapter number and metadata. ? june 2007, v2.4 added note 4 to table 2?4 .? december 2006 v2.3 updated table 2?1, table 2?4, and table 2?11. added revision history. ? march 2006, v2.2 updated table 2?1, table 2?9, table 2?13. updated figure 2?5 and figure 2?6. ? october 2005, v2.1 updated graphics. ? may 2005, v2.0 added table 2?1. updated hcell information for dsp functions in the functional description section. updated table 2?9. updated figures 2?4, 2?5, and 2?6. ? january 2005, v1.0 added document to the hardcopy series handbook. ?
altera corporation 3?1 september 2008 preliminary 3. boundary-scan support ieee std. 1149.1 (jtag) boundary-scan support all hardcopy ? ii structured asics provide joint test action group (jtag) boundary-scan test (bst) circui try that complies with the ieee std. 1149.1-1990 specification. the bst ar chitecture offers the capability to efficiently test compon ents on printed circuit boards (pcbs) with tight lead spacing by testing pin connect ions, without using physical test probes, and capturing functional data while a device is in normal operation. boundary-scan cells in a device can force signals onto pins, or capture data from pin or core logic signals. forced test data is serially shifted into the boundary-scan cells. ca ptured data is serially shifted out and externally compared to expected results. a device using the jtag interface uses four required pins, tdi , tdo , tms , and tck , and one optional pin, trst . the tck pin has an internal weak pull-down resistor, while the tdi , tms , and trst pins have weak internal pull-up resistors. the tdo output is powered by v ccio . hardcopy ii devices support the jtag instructions shown in table 3?1 . table 3?1. hardcopy ii jtag instructions (part 1 of 2) jtag instruction instr uction code description sample/preload 00 0000 0101 allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. extest (1) 00 0000 1111 allows the external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. bypass 11 1111 1111 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation. h51017-2.4
3?2 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 f the bsdl files for hardcopy ii devices are different from the corresponding stratix ? ii fpgas. for more information, or to receive bsdl files for ieee std. 1149.1- comp liant hardcopy ii devices, visit the altera website at www.altera.com . the hardcopy ii device instruction register length is 10 bits and the usercode register length is 32 bits. the usercode registers are not reprogrammable and are mask-programmed. the designer can choose an appropriate 32 bit sequence whic h will be programmed into the usercode registers. usercode 00 0000 0111 selects the 32-bit usercode register and places it between the tdi and tdo pins, allowing the usercode to be serially shifted out of tdo . idcode 00 0000 0110 selects the idcode register and places it between tdi and tdo , allowing the idcode to be serially shifted out of tdo . highz (1) 00 0000 1011 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the i/o pins. clamp (1) 00 0000 1010 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation while holding i/o pins to a state defined by the data in the boundary-scan register. note to ta b l e 3 ? 1 : (1) bus hold and weak pull-up resistor featur es override the high-impedance state of highz , clamp , and extest . table 3?1. hardcopy ii jtag instructions (part 2 of 2) jtag instruction instr uction code description
altera corporation 3?3 september 2008 preliminary ieee std. 1149.1 (jtag) boundary-scan support tables 3?2 and 3?3 show the boundary-scan register length and device idcode information for hardcopy ii devices. boundary-scan test (bst ) on hardcopy ii devices in order to run the boundary-scan test on hardcopy ii devices, you need two files: 1. the generic hardcopy ii bsdl file you can download from the altera website at www.altera.com . 2. the pin file for your design from the quartus ii software. with these two files, you must run through a tool called the bsdlcustomizer. table 3?2. hardcopy ii boundary-scan register length device boundary-scan register length hc210w 1050 hc210 1050 hc220 1530 HC230 2154 hc240 2910 table 3?3. 32-bit hardcopy ii device idcode device idcode (32 bits) (1) version (4 bits) part number (16 bits) manufacturer identity (11 bits) lsb (1 bit) (2) hc210w 0000 0010 0000 1100 0001 000 0110 1110 1 hc210 0000 0010 0000 1100 0010 000 0110 1110 1 hc220 0000 0010 0000 1100 0011 000 0110 1110 1 HC230 0000 0010 0000 1100 0100 000 0110 1110 1 hc240 0000 0010 0000 1100 0101 000 0110 1110 1 notes to ta b l e 3 ? 3 : (1) the most significant bit (msb) is on the left. (2) the least significant bit (lsb) of idcode is always 1 .
3?4 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 bsdlcustomizer is a tcl script which is used to modify the bsdl file?s port definitions and boundary-scan ch ain groups? attributes according to the design and pin assignments from the quartus ii software pin file. once you run the generic bsdl file and your pin file through the bsdlcustomizer tool, a modi fied bsdl file is created which should be used for the boundary-scan test. before running the boundary scan test on your board make sure that the nconfig pin is externally pulled low and that the nstatus pin is low. for more information on the bs dlcustomizer tool, refer to the bsdlcustomizer user guide that you can download with the bsdlcustomizer tool from the altera website at www.altera.com . figure 3?1 shows the timing requiremen ts for the jtag signals. figure 3?1. hardcopy ii jtag waveforms table 3?4 shows the jtag timing parameters and values for hardcopy ii devices. table 3?4. hardcopy ii jtag timing parameters and values (part 1 of 2) symbol parameter min max unit t jcp tck clock period 30 ns t jch tck clock high time 13 ns t jcl tck clock low time 13 ns t jpsu jtag port setup time 3 ns tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi
altera corporation 3?5 september 2008 preliminary document revision history f for more information on jtag or boundary-scan testing, refer to an 39: ieee std. 1149.1 (jtag ) boundary-scan testin g in altera devices . 1 like stratix ii fpgas, hardcopy ii devices support the signaltap? ii embedded logic an alyzer, which monitors design operation over a period of time through the jtag interface. the signaltap ii logic analyzer is a useful feature during the fpga prototyping phase, but should be removed if not needed once the design has been migrated to a hardcopy ii device. hardcopy ii is a mask programmed device, and the signal tap logic cannot be eliminated after the hardcopy ii device is fabricated. document revision history table 3?5 shows the revision history for this chapter. t jph jtag port hold time 5 ns t jpco jtag port clock to output 11 ns t jpzx jtag port high impedance to valid output 14 ns t jpxz jtag port valid output to high impedance 14 ns t jssu capture register setup time 4 ns t jsh capture register hold time 5 ns table 3?4. hardcopy ii jtag timing parameters and values (part 2 of 2) symbol parameter min max unit table 3?5. document revision history (part 1 of 2) date and document version changes made summary of changes september 2008, v2.4 updated chapter number and metadata. ? june 2007, v2.3 added resource information figure 3?1 changes new section on boundary-scan test (bst) on hardcopy ii devices. ? december 2006 v2.2 minor updates for quartus ii 6.1.0 software version added revision history updated for quartus ii 6.1 software version. october 2005, v2.1 updated graphics. ?
3?6 altera corporation preliminary september 2008 hardcopy series handbook, volume 1 may 2005, v2.0 updated table 3-2. ? january 2005 v1.0 added document to the hardcopy series handbook. ? table 3?5. document revision history (part 2 of 2) date and document version changes made summary of changes
altera corporation 4?1 september 2008 preliminary 4. dc and switching specifications and operating conditions introduction this chapter provides preliminary information on absolute maximum ratings, recommended operating conditions, dc electrical characteristics, and other specifications for hardcopy ? ii devices. absolute maximum ratings hardcopy ii devices are offered in both commercial and industrial grades. all parameter limits are re presentative of worst-case supply voltage and junction temperature con ditions. unless otherwise noted, the parameter values in this chapter apply to all hardcopy ii devices. table 4?1 contains the absolute maximum ratings for the hardcopy ii device family. table 4?1. hardcopy ii device absolute maximum ratings notes (1) , (2) , (3) symbol parameter conditions minimum maximum unit v ccint supply voltage with respect to ground -0.5 1.8 v v ccio supply voltage with respect to ground -0.5 4.6 v v ccpd supply voltage with respect to ground -0.5 4.6 v v cca analog power supply for plls with respect to ground -0.5 1.8 v v ccd digital power supply for plls with respect to ground -0.5 1.8 v v i dc input voltage(4) ? -0.5 4.6 v i out dc output current, per pin ? -25 40 ma t stg storage temperature no bias -65 150 c t j junction temperature ball-grid array (bga) packages under bias -55 125 c notes to ta b l e 4 ? 1 : (1) refer to the operating requirements for altera devices data sheet for more information. (2) conditions beyond those listed in table 4?1 may cause permanent damage to a device. additionally, device operation at the absolute maximum ratings for extended pe riods of time may have adve rse effects on the device. (3) supply voltage specifications apply to voltage readin gs taken at the device pins, not at the power supply. (4) during transitions, the inputs may overshoot to the voltage shown in table 4?2 based upon the input duty cycle. the dc case is equivalent to a 100% duty cycle. during transitions, the inputs may un dershoot to ?2.0 v for input currents less than 100 ma an d periods shorter than 20 ns. h51018-3.3
4?2 altera corporation september 2008 hardcopy series handbook, volume 1 recommended operating conditions table 4?3 contains the hardcopy ii device family?s recommended operating conditions. table 4?2. maximum duty cycles in voltage transitions v in (v) maximum duty cycles 4 100% 4.1 90% 4.2 50% 4.3 30% 4.4 17% 4.5 10% table 4?3. hardcopy ii device recommended operating conditions note (1) (part 1 of 2) symbol parameter conditions minimum maximum unit v ccint supply voltage for internal logic and input buffers 100 s rise time 100 ms (2) 1.15 1.25 v v ccio supply voltage for output buffers, 3.3-v operation 100 s rise time 100 ms (2) , (6) 3.135 (3.0) 3.465 (3.6) v supply voltage for output buffers, 2.5-v operation 100 s rise time 100 ms (2) 2.375 2.625 v supply voltage for output buffers, 1.8-v operation 100 s rise time 100 ms (2) 1.71 1.89 v supply voltage for output buffers, 1.5-v operation 100 s rise time 100 ms (2) 1.425 1.575 v v ccpd supply voltage for pre-drivers as well as configuration and jtag i/o buffers 100 s rise time 100 ms (3) 3.135 3.465 v v cca analog power supply for plls 100 s rise time 100 ms (3) 1.15 1.25 v v ccd digital power supply for plls 100 s rise time 100 ms (3) 1.15 1.25 v v i input voltage (4) , (5) -0.5 4.0 v v o output voltage ? 0 v ccio v
altera corporation 4?3 september 2008 dc electrical characteristics dc electrical characteristics table 4?4 shows the hardcopy ii device family?s dc electrical characteristics. t j operating junction temperature for commercial use 0 85 c for industrial use -40 100 c notes to ta b l e 4 ? 3 : (1) supply voltage specifications apply to voltage readin gs taken at the device pins, not at the power supply. (2) maximum v cc rise time is 100 ms, and v cc must rise monotonically. (3) v ccpd must ramp-up from 0 v to 3.3 v within 100 s to 100 ms. if v ccpd is not ramped up within this specified time, the hardcopy ii device will not power up successfully. (4) during transitions, the inputs may overshoot to the voltage shown in table 4?2 based upon the input duty cycle. the dc case is equivalent to a 100% duty cycle. during transitions, the inputs may un dershoot to ?2.0 v for input currents less than 100 ma and periods shorter than 20 ns. (5) all pins, including dedicated inputs, clock, i/o, and jtag pins, may be driven before v ccint , v ccpd , and v ccio are powered. (6) v ccio maximum and minimum conditions for pci and pci-x are shown in parentheses. table 4?3. hardcopy ii device recommended operating conditions note (1) (part 2 of 2) symbol parameter conditions minimum maximum unit table 4?4. hardcopy ii devi ce dc operating conditions note (1) (part 1 of 2) symbol parameter conditions device minimum typical maximum unit i i input pin leakage current v i = v ccio max to 0 v (2) all -10 ? 10 a i oz tri-stated i/o pin leakage current v o = v ccio max to 0 v (2) all -10 ? 10 a i ccint0 v ccint supply current (standby) v i = ground, no load, no toggling inputs t j = 25 c hc210w ? 0.09 (3) (5) a hc210 ? 0.09 (3) (5) a hc220 ? 0.19 (3) (5) a HC230 ? 0.34 (3) (5) a hc240 ? 0.52 (3) (5) a i ccpd0 v ccpd supply current (standby) v i = ground, no load, no toggling inputs t j = 25 c v ccpd = 3.3 v hc210w ? 3 (3) (5) ma hc210 ? 3 (3) (5) ma hc220 ? 4 (3) (5) ma HC230 ? 5 (3) (5) ma hc240 ? 5 (3) (5) ma
4?4 altera corporation september 2008 hardcopy series handbook, volume 1 i/o standard specifications tables 4?5 through 4?27 show the hardcopy ii device family?s i/o standard specifications. i ccio0 v ccio supply current (standby) v i = ground, no load, no toggling inputs t j = 25 c hc210w ? 3 (3) (5) ma hc210 ? 3 (3) (5) ma hc220 ? 3 (3) (5) ma HC230 ? 3 (3) (5) ma hc240 ? 3 (3) (5) ma r conf (4) value of i/o pin pull-up resistor before and during configuration v i = 0; v ccio = 3.3 v ? 10 25 50 k v i = 0; v ccio = 2.5 v ? 15 35 70 k v i = 0; v ccio = 1.8 v ? 30 50 100 k v i = 0; v ccio = 1.8 v ? 40 75 150 k v i = 0; v ccio = 1.2 v ? 50 90 170 k recommended value of i/o pin external pull-down resistor before and during configuration ???12k ? ? ? notes to ta b l e 4 ? 4 : (1) typical values are for ta = 25 c, v ccint = 1.2 v, and v ccio = 1.5-, 1.8-, 2.5-, and 3.3-v. (2) this value is specified for normal device operation. the value may vary during power-up. this applies for all v ccio settings (3.3-, 2.5-, 1.8-, and 1.5-v). (3) this specification is preliminary and pending further device characterization. (4) pin pull-up resistor values will lower if an external source drives the pin higher than v ccio . (5) maximum values depend on the actual t j and design utilization. see the powerplay early power estimator or the quartus ii powerplay power analyzer feature for maximum values. table 4?4. hardcopy ii devi ce dc operating conditions note (1) (part 2 of 2) symbol parameter conditions device minimum typical maximum unit table 4?5. lvttl specifications (part 1 of 2) symbol parameter conditions minimum maximum unit v ccio (1) output-supply voltage ? 3.135 3.465 v v ih high-level input voltage ? 1.7 4.0 v v il low-level input voltage ? -0.3 0.8 v v oh high-level output voltage i oh = -4 ma (2) , (3) 2.4 ? v
altera corporation 4?5 september 2008 i/o standard specifications v ol low-level output voltage i ol = 4 ma (2) , (3) ?0.45v notes to ta b l e 4 ? 5 : (1) hardcopy ii devices comply to the narrow range for the supply voltage as specified in the eia/jedec standard, jesd8-b. (2) drive strength is programmable according to values in table 2?10 , table 2?12 , and tab le 2?14 . (3) drive strength varies based on pin location. refer to the description, architecture, and features chapter in the hardcopy ii device family data sheet section of volume 1 of the hardcopy series handbook for more information. table 4?5. lvttl specifications (part 2 of 2) symbol parameter conditions minimum maximum unit table 4?6. lvcmos specifications symbol parameter conditions minimum maximum unit v ccio (1) output-supply voltage ? 3.135 3.465 v v ih high-level input voltage ? 1.7 4.0 v v il low-level input voltage ? -0.3 0.8 v v oh high-level output voltage v ccio = 3.0, i oh = -0.1 ma (2) , (3) v ccio ? 0.2 ? v v ol low-level output voltage v ccio = 3.0, i ol = 0.1 ma (2) , (3) ?0.2v notes to ta b l e 4 ? 6 : (1) hardcopy ii devices comply to the narrow range for the supply voltage as specified in the eia/jedec standard, jesd8-b. (2) drive strength is programmable according to values in tables 2?10 , 2?12 , and 2?14 . (3) drive strength varies based on pin location. refer to the description, architecture, and features chapter in the hardcopy ii device family data sheet section in volume 1 of the hardcopy series handbook for more information. table 4?7. 2.5-v i/o spec ifications (part 1 of 2) symbol parameter conditions minimum maximum unit v ccio (1) output-supply voltage ? 2.375 2.625 v v ih high-level input voltage ? 1.7 4.0 v v il low-level input voltage ? -0.3 0.7 v v oh high-level output voltage i oh = -1 ma (2) , (3) 2.0 ? v
4?6 altera corporation september 2008 hardcopy series handbook, volume 1 v ol low-level output voltage i ol = 1 ma (2) , (3) ?0.4v notes to ta b l e 4 ? 7 : (1) hardcopy ii devices v ccio voltage-level support of 2.5 -5% is narr ower than defined in the normal range of the eia/jedec standard. (2) drive strength is programmable according to values in tables 2?10 , 2?12 , and 2?14 . (3) drive strength varies based on pin location. refer to the description, architecture, and features chapter in the hardcopy ii device family data sheet section in volume 1 of the hardcopy series handbook for more information. table 4?7. 2.5-v i/o spec ifications (part 2 of 2) symbol parameter conditions minimum maximum unit table 4?8. 1.8-v i/ o specifications symbol parameter conditions minimum maximum unit v ccio (1) output-supply voltage ? 1.71 1.89 v v ih high-level input voltage ? 0.65 v ccio 2.25 v v il low-level input voltage ? -0.3 0.35 v ccio v v oh high-level output voltage i oh = -2 to -8 ma (2) , (3) v ccio ? 0.45 ? v v ol low-level output voltage i ol = 2 to 8 ma (2) , (3) ?0.45v notes to ta b l e 4 ? 8 : (1) hardcopy ii devices v ccio voltage-level support of 1.8 -5% is narr ower than defined in the normal range of the eia/jedec standard. (2) drive strength is programmable according to values in tables 2?10 , 2?12 , and 2?14 . (3) drive strength varies based on pin location. refer to the description, architecture, and features chapter in the hardcopy ii device family data sheet section in volume 1 of the hardcopy series handbook for more information. table 4?9. 1.5-v i/o spec ifications (part 1 of 2) symbol parameter conditions minimum maximum unit v ccio (1) output-supply voltage ? 1.425 1.575 v v ih high-level input voltage ? 0.65 v ccio v ccio + 0.3 v v il low-level input voltage ? -0.3 0.35 v ccio v v oh high-level output voltage i oh = -2 ma (2) , (3) 0.75 v ccio ?v
altera corporation 4?7 september 2008 i/o standard specifications figure 4?1 and figure 4?2 show receiver input and transmitter waveforms, respectively, for all differential i/o lvpecl and hypertransport technology. figure 4?1. receiver input waveform s for differential i/o standards v ol low-level output voltage i ol = 2 ma (2) , (3) ? 0.25 v ccio v notes to ta b l e 4 ? 9 : (1) hardcopy ii devices v ccio voltage-level support of 1.5 -5% is narr ower than defined in the normal range of the eia/jedec standard. (2) drive strength is programmable according to values in tables 2?10 , 2?12 , and 2?14 . (3) drive strength varies based on pin location. refer to the description, architecture, and features chapter in the hardcopy ii device family data sheet section in volume 1 of the hardcopy series handbook for more information. table 4?9. 1.5-v i/o spec ifications (part 2 of 2) symbol parameter conditions minimum maximum unit single-ended waveform differential waveform (mathematical function of positive & negative channel) positive channel (p) = v ih negative channel (n) = v il ground v id v id v id p ? n = 0 v v cm v id (peak-to-peak)
4?8 altera corporation september 2008 hardcopy series handbook, volume 1 figure 4?2. transmiter output wavefo rms for differential i/o standards single-ended waveform differential waveform (mathematical function of positive & negative channel) positive channel (p) = v oh negative channel (n) = v ol ground v od v od v od p ? n = 0 v v cm table 4?10. 2.5-v lvds i/o specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage for i/o banks that support high-speed ioes (1) , (2) ? 2.375 2.5 2.625 v ? v id input differential voltage swing (single-ended) ? 100 350 900 mv v icm input common mode voltage ? 200 1,250 1,800 mv v od output differential voltage (single-ended) r l = 100 250 ? 450 mv v ocm output common mode voltage r l = 100 1.125 ? 1.375 v r l receiver differential input discrete resistor (external to hardcopy ii devices) ? 90 100 110 notes to table 4?10 : (1) ioes = i/o elements. (2) for information on which i/o banks support high-speed ioes, refer to the description, architecture, and features chapter in the hardcopy ii device family data sheet section in volume 1 of the hardcopy series handbook.
altera corporation 4?9 september 2008 i/o standard specifications table 4?11. 3.3-v lvds i/o specifications note (1) symbol parameter conditions minimum typical maximum unit v ccio output and feedback pins in pll banks 9, 10, 11, and 12 (2) ? 3.135 3.3 3.465 v v id input differential voltage swing (single-ended) ? 100 350 900 mv v icm input common mode voltage ? 200 1,250 1,800 mv v od output differential voltage (single-ended) r l = 100 250 ? 710 mv v ocm output common mode voltage r l = 100 0.84 ? 1.570 v r l receiver differential input discrete resistor (external to hardcopy ii devices) ? 90 100 110 notes to ta b l e 4 ? 11 : (1) like stratix ii devices, 3.3-v lvds is supported by the top and bottom clock input differential buffers, and by the pll clock output and feedback pins. (2) the top and bottom clock input differential buffer s in i/o banks 3, 4, 7, and 8 are powered by v ccint , not v ccio . the pll clock output and feedback differential buffers are powered by vcc_pllout . for differential clock output and feedback oper ation, connect vcc_pllout to 3.3 v. table 4?12. lvpecl specifications (part 1 of 2) note (1) symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage for i/o banks that support high- speed ioes (2) ? 3.135 3.3 3.465 v v id (peak- to-peak) input differential voltage swing (single-ended) ? 300 600 1,000 mv v icm input common mode voltage r l = 100 1.0 ? 2.5 mv v od output differential voltage (single-ended) r l = 100 525 ? 970 mv v ocm output common mode voltage r l = 100 1.650 ? 2.275 v
4?10 altera corporation september 2008 hardcopy series handbook, volume 1 r l receiver differential input discrete resistor (external to hardcopy ii devices) ? 90 100 110 notes to table 4?12 : (1) like stratix ii devices, lvpecl is su pported by the top and bottom clock inpu t differential buffers, and by the pll clock output and feedback pins. (2) the top and bottom clock input differential buffer s in i/o banks 3, 4, 7, and 8 are powered by v ccint , not v ccio . the pll clock output and feedback di fferential buffers are powered by vcc_pllout . for differential clock output and feedback oper ation, connect vcc_pllout to 3.3 v. table 4?12. lvpecl specifications (part 2 of 2) note (1) symbol parameter conditions minimum typical maximum unit table 4?13. hypertransport tec hnology specifications symbol parameter conditions min imum typical maximum unit v ccio i/o supply voltage for i/o banks that support high-speed ioes (1) , (2) ? 2.375 2.5 2.625 v output and feedback pins in pll banks 9, 10, 11, and 12 ? 3.135 3.3 3.465 v v id (peak- to-peak) input differential voltage swing (single-ended) ? 300 600 900 mv v icm input common mode voltage ? 385 600 845 mv v od output differential voltage (single-ended) r l = 100 400 600 820 mv v od change in v od between high and low r l = 100 ?? 75mv v ocm output common mode voltage r l = 100 440 600 780 v v ocm change in v ocm between high and low r l = 100 ?? 50mv r l receiver differential input discrete resistor (external to hardcopy ii devices) ? 90 100 110 notes to table 4?13 : (1) for information on which i/o banks support high-speed ioes, refer to the description, architecture, and features chapter in the hardcopy ii device family data sheet section in volume 1 of the hardcopy series handbook. (2) the top and bottom clock input differential buffer s in i/o banks 3, 4, 7, and 8 are powered by v ccint , not v ccio . the pll clock output and feedback di fferential buffers are powered by vcc_pllout . for differential clock output and feedback oper ation, connect vcc_pllout to 3.3 v.
altera corporation 4?11 september 2008 i/o standard specifications table 4?14. 3.3-v pci specifications symbol parameter conditions mi nimum typical maximum unit v ccio output-supply voltage ? 3 3.3 3.6 v v ih high-level input voltage ? 0.5 v ccio ?v ccio + 0.5 v v il low-level input voltage ? -0.3 ? 0.3 v ccio v v oh high-level output voltage i out = -500 a 0.9 v ccio ??v v ol low-level output voltage i out = 1,500 a ? ? 0.1 v ccio v table 4?15. pci-x mode 1 specifications symbol parameter conditions mi nimum typical maximum unit v ccio output-supply voltage ? 3 ? 3.6 v v ih high-level input voltage ? 0.5 v ccio ?v ccio + 0.5 v v il low-level input voltage ? -0.3 ? 0.35 vccio v v ipu input pull-up voltage ? 0.7 v ccio ??v v oh high-level output voltage i out = -500 a 0.9 v ccio ??v v ol low-level output voltage i out = 1,500 a ? ? 0.1 v ccio v table 4?16. sstl-18 class i s pecifications (part 1 of 2) symbol parameter conditions minimum typical maximum unit v ccio output-supply voltage ? 1.71 1.8 1.89 v v ref reference voltage ? 0.855 0.9 0.945 v v tt termination voltage ? v ref ? 0.04 vref v ref + 0.04 v v ih(dc) high-level dc input voltage ? v ref + 0.125 ? ? v v il(dc) low-level dc input voltage ? ? ? v ref ? 0.125 v v ih(ac) high-level ac input voltage ? v ref + 0.25 ? ? v v il(ac) low-level ac input voltage ? ? ? v ref ? 0.25 v v oh high-level output voltage i oh = -6.7 ma (1) , (2) v tt + 0.475 ? ? v
4?12 altera corporation september 2008 hardcopy series handbook, volume 1 v ol low-level output voltage i ol = 6.7 ma (1) , (2) ??v tt ? 0.475 v notes to table 4?16 : (1) this specification is supported across all the programmab le drive settings available fo r this i/o standard as shown in the i/o structure and features section located in the description, architecture, and features chapter in volume 1 of the hardcopy series devices handbook. (2) drive strength varies based on pin location. refer to the description, architecture, and features chapter in the hardcopy ii device family data sheet section in volume 1 of the hardcopy series handbook for more information. table 4?16. sstl-18 class i s pecifications (part 2 of 2) symbol parameter conditions minimum typical maximum unit table 4?17. sstl-18 clas s ii specifications symbol parameter conditions minimum typical maximum unit v ccio output-supply voltage ? 1.71 1.8 1.89 v v ref reference voltage ? 0.855 0.9 0.945 v v tt termination voltage ? v ref ? 0.04 v ref v ref + 0.04 v v ih(dc) high-level dc input voltage ? v ref + 0.125 ? ? v v il(dc) low-level dc input voltage ? ? ? v ref ? 0.125 v v ih(ac) high-level ac input voltage ? v ref + 0.25 ? ? v v il(ac) low-level ac input voltage ? ? ? v ref ? 0.25 v v oh high-level output voltage i oh = -13.4 ma (1) , (2) v tt ? 0.28 ? ? v v ol low-level output voltage i ol = 13.4 ma (1) , (2) ??0.28v notes to table 4?17 : (1) this specification is supported across all the programmable drive settings available for this i/o standard as shown in the i/o structure and features section located in the description, architecture, and features chapter in volume 1 of the hardcopy series devices handbook. (2) drive strength varies based on pin location. refer to the description, architecture, and features chapter in the hardcopy ii device family data sheet section in volume 1 of the hardcopy series handbook for more information. table 4?18. sstl-18 differential specifications (part 1 of 2) symbol parameter conditions minimum typical maximum unit v ccio output-supply voltage ? 1.71 1.8 1.89 v v swing(dc) dc differential input voltage ? 0.25 ? ? v
altera corporation 4?13 september 2008 i/o standard specifications v x(ac) ac differential input cross point voltage ?(v ccio/2 ) ? 0.175 ? (v ccio/2 ) + 0.175 v v swing(ac) ac differential input voltage ? 0.5 ? ? v v iso input clock signal offset voltage ? ? 0.5 v ccio ?v v iso input clock signal offset voltage variation ? ? 200 ? v v ox(ac) ac differential cross point voltage ?(v ccio/2 ) ? 0.125 ? (v ccio/2 ) + 0.125 v table 4?18. sstl-18 differential specifications (part 2 of 2) symbol parameter conditions minimum typical maximum unit table 4?19. sstl-2 class i specifications symbol parameter conditions mi nimum typical maximum unit v ccio output-supply voltage ? 2.375 2.5 2.625 v v tt termination voltage ? v ref ? 0.04 v ref v ref + 0.04 v v ref reference voltage ? 1.188 1.25 1.313 v v ih (dc) high-level input voltage ? v ref + 0.18 ? 3.0 v v il (dc) low-level input voltage ? -0.3 ? v ref ? 0.18 v v ih (ac) high-level input voltage ? v ref + 0.35 ? ? v v il (ac) low-level input voltage ? ? ? v ref ? 0.35 v v oh high-level output voltage i oh = -8.1 ma (1) , (2) v tt + 0.57 ? ? v v ol low-level output voltage i ol = 8.1 ma (1) , (2) ??v tt ? 0.57 v notes to table 4?19 : (1) this specification is supported across all the programmab le drive settings available fo r this i/o standard as shown in the i/o structure and features section of the description, architecture, and features chapter in volume 1 of the hardcopy series devices handbook. (2) drive strength varies based on pin location. refer to the description, architecture, and features chapter in the hardcopy ii device family data sheet section in volume 1 of the hardcopy series handbook for more information.
4?14 altera corporation september 2008 hardcopy series handbook, volume 1 table 4?20. sstl-2 class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output-supply voltage ? 2.375 2.5 2.625 v v tt termination voltage ? v ref ? 0.04 v ref v ref + 0.04 v v ref reference voltage ? 1.188 1.25 1.313 v v ih (dc) high-level input voltage ? v ref + 0.18 ? v ccio + 0.3 v v il (dc) low-level input voltage ? -0.3 ? v ref ? 0.18 v v ih (ac) high-level input voltage ? v ref + 0.35 ? ? v v il (ac) low-level input voltage ? ? ? v ref ? 0.35 v v oh high-level output voltage i oh = -16.4 ma (1) , (2) v tt + 0.76 ? ? v v ol low-level output voltage i ol = 16.4 ma (1) , (2) ??v tt ? 0.76 v notes to table 4?20 : (1) this specification is supported across all the programmab le drive settings available fo r this i/o standard as shown in the i/o structure and features section located in the description, architecture, and features chapter in volume 1 of the hardcopy series devices handbook. (2) drive strength varies based on pin location. refer to the description, architecture, and features chapter in the hardcopy ii device family data sheet section in volume 1 of the hardcopy series handbook for more information. table 4?21. sstl-2 differ ential specifications symbol parameter conditions minimum typical maximum unit v ccio output-supply voltage ? 2.375 2.5 2.625 v v swing (dc) dc differential input voltage ? 0.36 ? ? v v x (ac) ac differential input cross point voltage ?(v ccio/2 ) ? 0.2 ? (v ccio/2 ) + 0.2 v v swing (ac) ac differential input voltage ? 0.7 ? ? v v iso input clock signal offset voltage ? ? 0.5 v ccio ?v v iso input clock signal offset voltage variation ? ? 200 ? v v ox (ac) ac differential output cross point voltage ?(v ccio/2 ) ? 0.2 ? (v ccio/2 ) + 0.2 v
altera corporation 4?15 september 2008 i/o standard specifications table 4?22. 1.5-v hstl cl ass i specifications symbol parameter conditions mi nimum typical maximum unit v ccio output-supply voltage ? 1.425 1.5 1.575 v v ref input reference voltage ? 0.713 0.75 0.788 v v tt termination voltage ? 0.713 0.75 0.788 v v ih (dc) dc high-level input voltage ? v ref + 0.1 ? ? v v il (dc) dc low-level input voltage ? -0.3 ? v ref ? 0.1 v v ih (ac) ac high-level input voltage ? v ref + 0.2 ? ? v v il(ac) ac low-level input voltage ? ? ? v ref ? 0.2 v v oh high-level output voltage i oh = 8 ma (1) , (2) v ccio ? 0.4 ? ? v v ol low-level output voltage i ol = -8 ma (1) , (2) ??0.4v notes to table 4?22 : (1) this specification is supported across all the programmab le drive settings available fo r this i/o standard as shown in the i/o structure and features section located in the description, architecture, and features chapter in volume 1 of the hardcopy series devices handbook. (2) drive strength varies based on pin location. refer to the description, architecture, and features chapter in the hardcopy ii device family data sheet section in volume 1 of the hardcopy series handbook for more information. table 4?23. 1.5-v hstl class ii specifications (part 1 of 2) symbol parameter conditions minimum typical maximum unit v ccio output-supply voltage ? 1.425 1.5 1.575 v v ref input reference voltage ? 0.713 0.75 0.788 v v tt termination voltage ? 0.713 0.75 0.788 v v ih (dc) dc high-level input voltage ? v ref + 0.1 ? ? v v il (dc) dc low-level input voltage ? -0.3 ? v ref ? 0.1 v v ih (ac) ac high-level input voltage ? v ref + 0.2 ? ? v v il (ac) ac low-level input voltage ? ? ? v ref ? 0.2 v v oh high-level output voltage i oh = 16 ma (1) , (2) v ccio ? 0.4 ? ? v
4?16 altera corporation september 2008 hardcopy series handbook, volume 1 v ol low-level output voltage i ol = -16 ma (1) , (2) ??0.4v notes to table 4?23 : (1) this specification is supported across all the programmable drive settings available for this i/o standard as shown inthe i/o structure and features section of the description, architecture, and features chapter in volume 1 of the hardcopy series devices handbook. (2) drive strength varies based on pin location. refer to the description, architecture, and features chapter in the hardcopy ii device family data sheet section in volume 1 of the hardcopy series handbook for more information. table 4?23. 1.5-v hstl class ii specifications (part 2 of 2) symbol parameter conditions minimum typical maximum unit table 4?24. 1.5-v differential hstl specifications symbol parameter conditions mi nimum typical maximum unit v ccio i/o supply voltage ? 1.425 1.5 1.575 v v dif (dc) dc input differential voltage ? 0.2 ? ? v v cm (dc) dc common mode input voltage ? 0.68 ? 0.9 v v dif (ac) ac differential input voltage ? 0.4 ? ? v v ox (ac) ac differential cross point voltage ?0.68?0.9v table 4?25. 1.8-v hstl class i specifications (part 1 of 2) symbol parameter conditions minimum typical maximum unit v ccio output-supply voltage ? 1.71 1.8 1.89 v v ref input reference voltage ? 0.85 0.9 0.95 v v tt termination voltage ? 0.85 0.9 0.95 v v ih (dc) dc high-level input voltage ? v ref + 0.1 ? ? v v il (dc) dc low-level input voltage ? -0.3 ? v ref ? 0.1 v v ih( ac) ac high-level input ? v ref + 0.2 ? ? v v il (ac) ac low-level input voltage ? ? ? v ref ? 0.2 v v oh high-level output voltage i oh = 8 ma (1) , (2) v ccio ? 0.4 ? ? v
altera corporation 4?17 september 2008 i/o standard specifications v ol low-level output voltage i ol = -8 ma (1) , (2) ??0.4v notes to table 4?25 : (1) this specification is supported across all the programmabl e drive settings available for this i/o standard as shown in the i/o structure and features section located in the description, architecture, and features chapter of the hardcopy series devices handbook. (2) drive strength varies based on pin location. refer to the description, architecture, and features chapter in the hardcopy ii device family data sheet section in volume 1 of the hardcopy series handbook for more information. table 4?25. 1.8-v hstl class i specifications (part 2 of 2) symbol parameter conditions minimum typical maximum unit table 4?26. 1.8-v hstl cl ass ii speci fications symbol parameter conditions minimum typical maximum unit v ccio output-supply voltage ? 1.71 1.8 1.89 v v ref input reference voltage ? 0.85 0.9 0.95 v v tt termination voltage ? 0.85 0.9 0.95 v v ih (dc) dc high-level input voltage ? v ref + 0.1 ? ? v v il (dc) dc low-level input voltage ? -0.3 ? v ref ? 0.1 v v ih (ac) ac high-level input voltage ? v ref + 0.2 ? ? v v il (ac) ac low-level input voltage ? ? ? v ref ? 0.2 v v oh high-level output voltage i oh = 16 ma (1) , (2) v ccio ? 0.4 ? ? v v ol low-level output voltage i ol = -16 ma (1) , (2) ??0.4v notes to table 4?26 : (1) this specification is supported across all the programmab le drive settings available fo r this i/o standard as shown in the i/o structure and features section located in the description, architecture, and features chapter in volume 1 of the hardcopy series devices handbook. (2) drive strength varies based on pin location. refer to the description, architecture, and features chapter in the hardcopy ii device family data sheet section in volume 1 of the hardcopy series handbook for more information. table 4?27. 1.8-v differential hs tl specifications (part 1 of 2) symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage ? 1.71 1.8 1.89 v v dif (dc) dc input differential voltage ? 0.2 ? v ccio + 0.6 v v v cm (dc) dc common mode input voltage ? 0.78 ? 1.12 v
4?18 altera corporation september 2008 hardcopy series handbook, volume 1 bus hold specifications table 4?28 shows the hardcopy ii device family?s bus hold specifications. v dif (ac) ac differential input voltage ? 0.4 ? v ccio + 0.6 v v v ox (ac) ac differential cross point voltage ? 0.68 ? 0.9 v table 4?27. 1.8-v differential hs tl specifications (part 2 of 2) symbol parameter conditions minimum typical maximum unit table 4?28. bus hold parameters parameter conditions v ccio level unit 1.5 v 1.8 v 2.5 v 3.3 v min max min max min max min max low sustaining current v in > v il (maximum) 25 ? 30 ? 50 ? 70 ? a high sustaining current v in < v ih (minimum) - 25 ? -30 ? -50 ? -70 ? a low overdrive current 0 v < v in < v ccio ? 160 ? 200 ? 300 ? 500 a high overdrive current 0 v < v in < v ccio ? -160 ? -200 ? -300 ? -500 a bus-hold trip point ? 0.50 1.00 0.68 1.07 0.70 1.70 0.80 2.00 v
altera corporation 4?19 september 2008 on-chip termination specifications on-chip termination specifications table 4?29 defines the specification for internal termination specification when using series or differenti al on-chip termination for hc210w devices only. table 4?29. series on-chip termina tion specification for i/ o banks supporting memory interface ioes for hc210w notes (1) , (2) , (3) symbol description conditions resistance tolerance commercial max industrial max unit 25 r s 3.3/2.5 internal series termination with calibration (25- setting) v cc io = 3.3/2.5 v 10 15 % internal series termination without calibration (25- setting) v cc io = 3.3/2.5 v 30 30 % 50 r s 3.3/2.5 internal series termination with calibration (50- setting) v cc io = 3.3/2.5 v 10 15 % internal series termination without calibration (50- setting) v cc io = 3.3/2.5 v 30 30 % 25 r s 1.8 internal series termination with calibration (25- setting) v cc io = 1.8 v 10 15 % internal series termination without calibration (25- setting) v cc io = 1.8 v 30 30 % 50 r s 1.8 internal series termination with calibration (50- setting) v cc io = 1.8 v 10 15 % internal series termination without calibration (50- setting) v cc io = 1.8 v 30 30 % 50 r s 1.5 internal series termination with calibration (50- setting) v cc io = 1.5 v 13 15 % internal series termination without calibration (50- setting) v cc io = 1.5 v 36 36 % notes to table 4?29 : (1) for information on which i/o banks suppo rt memory interface ioes, refer to the description, architecture, and features chapter in the hardcopy ii device family data sheet section in volume 1 of the hardcopy series handbook. (2) the resistance tolerances for calibrate d soct and poct are at the time of init ial of calibration. if the temperature or voltage changes over time, the tolerance may also change. (3) this table applies only to the hc210w device.
4?20 altera corporation september 2008 hardcopy series handbook, volume 1 tables 4?30 and 4?31 define the specification for internal termination specification when using series or differential on-chip termination. table 4?30. series on-chip termination specificati on for i/o banks supporting memory interface ioes notes (1) , (2) , (3) symbol description conditions resistance tolerance commercial max industrial max unit 25 r s 3.3/2.5 internal series termination with calibration (25- setting) v cc io = 3.3/2.5 v 5 10 % internal series termination without calibration (25- setting) v cc io = 3.3/2.5 v 30 30 % 50 r s 3.3/2.5 internal series termination with calibration (50- setting) v cc io = 3.3/2.5 v 5 10 % internal series termination without calibration (50- setting) v cc io = 3.3/2.5 v 30 30 % 25 r s 1.8 internal series termination with calibration (25- setting) v cc io = 1.8v 5 10 % internal series termination without calibration (25- setting) v cc io = 1.8 v 30 30 % 50 r s 1.8 internal series termination with calibration (50- setting) v cc io = 1.8v 5 10 % internal series termination without calibration (50- setting) v cc io = 1.8 v 30 30 % 50 r s 1.5 internal series termination with calibration (50- setting) v cc io = 1.5 v 8 10 % internal series termination without calibration (50- setting) v cc io = 1.5 v 36 36 % notes to table 4?30 : (1) for information on which i/o banks suppo rt memory interface ioes, refer to the description, architecture, and features chapter in the hardcopy ii device family data sheet section in volume 1 of the hardcopy series handbook. (2) the resistance tolerances for calibrated soct and poct are at the time of initial calibration. if the temperature or voltage changes over time, the tolerance may also change. (3) this table applies only to hc210, hc220, HC230 and hc240 devices.
altera corporation 4?21 september 2008 pin capacitance pin capacitance table 4?32 shows the hardcopy ii device family?s pin capacitance. table 4?31. series and differential on-chip termi nation specification for i/o banks supporting high-speed and general purpose ioes notes (1) , (3) , (4) symbol description conditions resistance tolerance commercial max industrial max unit 25 r s 3.3/2.5 internal series termination without calibration (25- setting) v ccio = 3.3/2.5 v 30 30 % 50 r s 3.3/2.5/1.8 internal series termination without calibration (50- setting) v ccio = 3.3/2.5/1.8 v 30 30 % 50 r s 1.5 internal series termination without calibration (50- setting) v ccio = 1.5 v 36 36 % r d (2) internal differential termination for lvds or hypertransport technology ?2025% notes to table 4?31 : (1) for information on which i/o banks support high-speed ioes, refer to the description, architecture, and features chapter in the hardcopy ii device family data sheet section in volume 1 of the hardcopy series handbook. (2) r d is only supported on high-speed ioes. (3) the resistance tolerances for calibrated soct and poct are at the time of initial calibration. if the temperature or voltage changes over time, the tolerance may also change. (4) this table applies only to hc210, hc220, HC230, and hc240 devices. table 4?32. hardcopy ii device capacitance note (1) (part 1 of 2) symbol parameter hc210w typical hc210, hc220, HC230, hc240 typical unit c gpio input capacitance on i/o pins in i/o banks supporting general-purpose ioes. 5.7 5.0 pf c miio input capacitance on i/o pins in i/o banks supporting memory interface ioes. 5.7 5.0 pf c hsio input capacitance on i/o pins in i/o banks supporting high-speed ioes. 7.2 6.1 pf c clktb input capacitance on top/bottom clock input pins clk[4..7] and clk[12..15]. 6.0 6.0 pf
4?22 altera corporation september 2008 hardcopy series handbook, volume 1 maximum input clock rates tables 4?33 and 4?34 show the maximum input clocking rates of hardcopy ii i/os. c clklr input capacitance on left/right clock inputs clk0, clk2, clk8, clk10. 4.3 6.1 pf c clklr+ input capacitance on left/right clock inputs clk1, clk3, clk9, and clk11. 4.2 3.3 pf c outfb input capacitance on dual-purpose clock output/feedback pins in pll banks 9, 10, 11, and 12. 6.9 6.7 pf note to table 4?32 : (1) capacitance is sample-tested only. capacitance is me asured using time-domain reflections (tdr). measurement accuracy is within 0.5 pf. table 4?32. hardcopy ii device capacitance note (1) (part 2 of 2) symbol parameter hc210w typical hc210, hc220, HC230, hc240 typical unit table 4?33. hardcopy ii maximum input clock rate s of hc210, hc220, HC230 and hc240 devices (part 1 of 2) i/ostandard memory interface ioes high speed ioes general purpose ioes clk [0..3, 8..11] clk [4..7, 12..15] fpll_clk pll_fb unit lvttl 500 500 500 500 500 500 500 mhz 2.5 v 500 500 500 500 500 500 500 mhz 1.8 v 500 500 500 500 500 500 500 mhz 1.5 v 500 500 500 500 500 500 500 mhz lvcmos 500 500 500 500 500 500 500 mhz sstl2 class i 500 ? ? ? 500 ? 500 mhz sstl2 class ii 500 ? ? ? 500 ? 500 mhz sstl18 class i 500 ? ? ? 500 ? 500 mhz sstl18 class ii 500 ? ? ? 500 ? 500 mhz 1.5 v hstl class i 500 ? ? ? 500 ? 500 mhz 1.5 v hstl class ii 500 ? ? ? 500 ? 500 mhz 1.8 v hstl class i 500 ? ? ? 500 ? 500 mhz 1.8 v hstl class ii 500 ? ? ? 500 ? 500 mhz pci (1) 500 ? 500 ? 500 ? 500 mhz
altera corporation 4?23 september 2008 maximum input clock rates pci-x (1) 500 ? 500 ? 500 ? 500 mhz differential sstl2 class i (2) , (3) 500 ? ? ? 500 ? 500 mhz differential sstl2 class ii (2) , (3) 500 ? ? ? 500 ? 500 mhz differential sstl18 class i (2) , (3) 500 ? ? ? 500 ? 500 mhz differential sstl18 class ii (2) , (3) 500 ? ? ? 500 ? 500 mhz 1.8-v differential hstl class i (2) , (3) 500 ? ? ? 500 ? 500 mhz 1.8-v differential hstl class ii (2) , (3) 500 ? ? ? 500 ? 500 mhz 1.5-v differential hstl class i (2) , (3) 500 ? ? ? 500 ? 500 mhz 1.5-v differential hstl class ii (2) , (3) 500 ? ? ? 500 ? 500 mhz lvds ? 520 ? 717 450 717 450 mhz lvpecl ? ? ? ? 450 ? 450 mhz hypertransport ? 520 ? 717 ? 717 ? mhz notes to table 4?33 : (1) the pci clamping diode is only suppo rted on the top and bottom i/o pins. (2) this i/o standard is only supported on the dqs , clk , and pll_fb input pins. (3) for hc210 and hc220, differential hstl /sstl input is supported on top/bottom pll_fb , the top clock pins and dqs pins located on the top i/os. table 4?33. hardcopy ii maximum input clock rate s of hc210, hc220, HC230 and hc240 devices (part 2 of 2) i/ostandard memory interface ioes high speed ioes general purpose ioes clk [0..3, 8..11] clk [4..7, 12..15] fpll_clk pll_fb unit
4?24 altera corporation september 2008 hardcopy series handbook, volume 1 table 4?34. hardcopy ii maximum input clock rates of hc210w devices note (3) (part 1 of 2) i/o standard memory interface ioes high speed ioes general purpose ioes clk [0..3, 8..11] clk [4..7, 12..15] fpll_c lk pll_fb unit lvttl 350 350 350 350 350 350 350 mhz 2.5-v lvttl/lvcmos 350 350 350 350 350 350 350 mhz 1.8-v lvttl/lvcmos 350 350 350 350 350 350 350 mhz 1.5-v lvttl/lvcmos 270 270 270 270 270 270 270 mhz lvcmos 350 350 350 350 350 350 350 mhz sstl2 class i 350 ? ? ? 350 ? 350 mhz sstl2 class ii 350 ? ? ? 350 ? 350 mhz sstl18 class i 350 ? ? ? 350 ? 350 mhz sstl18 class ii 350 ? ? ? 350 ? 350 mhz 1.5-v hstl class i 350 ? ? ? 350 ? 350 mhz 1.5-v hstl class ii 350 ? ? ? 350 ? 350 mhz 1.8-v hstl class i 350 ? ? ? 350 ? 350 mhz 1.8-v hstl class ii 350 ? ? ? 350 ? 350 mhz pci (1) 315 ? 315 ? 315 ? 315 mhz pci-x (1) 315 ? 315 ? 315 ? 315 mhz differential sstl2 class i (2) ? ? ? ? 350 ? 350 mhz differential sstl2 class ii (2) ? ? ? ? 350 ? 350 mhz differential sstl18 class i (2) ? ? ? ? 350 ? 350 mhz differential sstl18 class ii (2) ? ? ? ? 350 ? 350 mhz 1.8-v differential hstl class i (2) ? ? ? ? 350 ? 350 mhz 1.8-v differential hstl class ii (2) ? ? ? ? 350 ? 350 mhz 1.5-v differential hstl class i (2) ? ? ? ? 350 ? 350 mhz 1.5-v differential hstl class ii (2) ? ? ? ? 350 ? 350 mhz lvds ? 320 ? 320 320 320 320 mhz lvpecl ? ? ? ? 320 ? 320 mhz
altera corporation 4?25 september 2008 maximum output clock rates maximum output clock rates tables 4?35 and 4?36 show the maximum output toggle rates of hardcopy ii i/o's for all available drive strengths. hypertransport ? 320 ? 320 ? 320 ? mhz notes to table 4?34 : (1) the pci clamping diode is only suppo rted on the top and bottom i/o pins. (2) for hc210w, differential hstl/sstl input is supported on the top clock pins, the dqs pins on the top i/o banks and top/bottom pll_fb input pins. (3) these numbers are preliminary and pe nding further silico n characterization. table 4?34. hardcopy ii maximum input clock rates of hc210w devices note (3) (part 2 of 2) i/o standard memory interface ioes high speed ioes general purpose ioes clk [0..3, 8..11] clk [4..7, 12..15] fpll_c lk pll_fb unit table 4?35. hardcopy ii maximum output cloc k rate of hc210, hc220, HC230 and hc240 devices note (1) (part 1 of 5) i/o standard drive strength memory interface ioes high speed ioes general purpose ioes clk [0, 2, 8, 10] (2) clk [4..7, 12..15] pll_out unit bottom column right row 3.3-v lvttl 4 ma 225 225 225 225 225 225 225 mhz 8 ma 355 355 355 355 355 355 355 mhz 12 ma 475 475 475 475 475 475 475 mhz 16 ma 594 ? ? ? ? 594 594 mhz 20 ma 700 ? ? ? ? 700 700 mhz 24 ma (3) 794 ? ? ? ? 794 794 mhz 3.3-v lvcmos 4 ma 250 250 250 250 250 250 250 mhz 8 ma 480 480 480 480 480 480 480 mhz 12 ma 710 ? ? ? ? 710 710 mhz 16 ma 925 ? ? ? ? 925 925 mhz 20 ma 985 ? ? ? ? 985 985 mhz 24 ma (3) 1040 ? ? ? ? 1040 1040 mhz
4?26 altera corporation september 2008 hardcopy series handbook, volume 1 2.5-v lv t t l / lv c m o s 4 ma 194 194 194 194 194 194 194 mhz 8 ma 380 380 380 380 380 380 380 mhz 12 ma 575 575 575 575 575 575 575 mhz 16 ma (3) 845 ? ? ? ? 845 845 mhz 1.8-v lv t t l / lv c m o s 2 ma 109 109 109 109 109 109 109 mhz 4 ma 250 250 250 250 250 250 250 mhz 6 ma 390 390 390 390 390 390 390 mhz 8 ma 570 570 570 570 570 570 570 mhz 10 ma 805 ? ? ? ? 805 805 mhz 12 ma (3) 1040 ? ? ? ? 1040 1040 mhz 1.5-v lv t t l / lv c m o s 2 ma 200 200 200 200 200 200 200 mhz 4 ma 370 370 370 370 370 370 370 mhz 6 ma 430 ? ? ? ? 430 430 mhz 8ma (3) 495 ? ? ? ? 495 495 mhz sstl2 class i 8 ma 300 ? ? ? ? 300 300 mhz 12 ma (3) 400 ? ? ? ? 400 400 mhz sstl2 class ii 16 ma 350 ? ? ? ? 350 350 mhz 20 ma 350 ? ? ? ? 350 350 mhz 24 ma (3) 400 ? ? ? ? 400 400 mhz sstl18 class i 4 ma 150 ? ? ? ? 150 150 mhz 6 ma 250 ? ? ? ? 250 250 mhz 8 ma 300 ? ? ? ? 300 300 mhz 10 ma 400 ? ? ? ? 400 400 mhz 12 ma (3) 550 ? ? ? ? 550 550 mhz sstl18 class ii 8 ma 200 ? ? ? ? 200 200 mhz 16 ma 350 ? ? ? ? 350 350 mhz 18 ma 400 ? ? ? ? 400 400 mhz 20 ma (3) 500 ? ? ? ? 500 500 mhz table 4?35. hardcopy ii maximum output cloc k rate of hc210, hc220, HC230 and hc240 devices note (1) (part 2 of 5) i/o standard drive strength memory interface ioes high speed ioes general purpose ioes clk [0, 2, 8, 10] (2) clk [4..7, 12..15] pll_out unit bottom column right row
altera corporation 4?27 september 2008 maximum output clock rates 1.8-v hstl class i 4 ma 300 ? ? ? ? 300 300 mhz 6 ma 450 ? ? ? ? 450 450 mhz 8 ma 600 ? ? ? ? 600 600 mhz 10 ma 650 ? ? ? ? 650 650 mhz 12 ma (3) 700 ? ? ? ? 700 700 mhz 1.8-v hstl class ii 16 ma 500 ? ? ? ? 500 500 mhz 18 ma 500 ? ? ? ? 500 500 mhz 20 ma (3) 550 ? ? ? ? 550 550 mhz 1.5-v hstl class i 4 ma 300 ? ? ? ? 300 300 mhz 6 ma 500 ? ? ? ? 500 500 mhz 8 ma 650 ? ? ? ? 650 650 mhz 10 ma 700 ? ? ? ? 700 700 mhz 12 ma (3) 700 ? ? ? ? 700 700 mhz 1.5-v hstl class ii 16 ma 600 ? ? ? ? 600 600 mhz 18 ma 600 ? ? ? ? 600 600 mhz 20 ma (3) 650 ? ? ? ? 650 650 mhz pci (4) ? 790 ? 790 ? ? 790 790 mhz pci-x (4) ? 790 ? 790 ? ? 790 790 mhz lvds ? ? 717 ? ? ? ? 400 mhz hypertransport ? ? 717 ? ? ? ? ? mhz lvpecl ? ? ? ? ? ? ? 400 mhz differential sstl2 class i (5) 8 ma 300 ? ? ? ? 300 300 mhz 12 ma (3) 400 ? ? ? ? 400 400 mhz differential sstl2 class ii (5) 16 ma 350 ? ? ? ? 350 350 mhz 20 ma (3) 350 ? ? ? ? 350 350 mhz 24 ma (3) 400 ? ? ? ? 400 400 mhz table 4?35. hardcopy ii maximum output cloc k rate of hc210, hc220, HC230 and hc240 devices note (1) (part 3 of 5) i/o standard drive strength memory interface ioes high speed ioes general purpose ioes clk [0, 2, 8, 10] (2) clk [4..7, 12..15] pll_out unit bottom column right row
4?28 altera corporation september 2008 hardcopy series handbook, volume 1 differential sstl18 class i (5) 4 ma 150 ? ? ? ? 150 150 mhz 6 ma 250 ? ? ? ? 250 250 mhz 8 ma 300 ? ? ? ? 300 300 mhz 10 ma 400 ? ? ? ? 400 400 mhz 12 ma (3) 550 ? ? ? ? 550 550 mhz differential sstl18 class ii (5) 8 ma 200 ? ? ? ? 200 200 mhz 16 ma 350 ? ? ? ? 350 350 mhz 18 ma 400 ? ? ? ? 400 400 mhz 20 ma (3) 500 ? ? ? ? 500 500 mhz 1.8-v differential hstl class i (5) 4 ma 300 ? ? ? ? 300 300 mhz 6 ma 450 ? ? ? ? 450 450 mhz 8 ma 600 ? ? ? ? 600 600 mhz 10 ma 650 ? ? ? ? 650 650 mhz 12 ma (3) 700 ? ? ? ? 700 700 mhz 1.8-v differential hstl class ii (5) 16 ma 500 ? ? ? ? 500 500 mhz 18 ma 500 ? ? ? ? 500 500 mhz 20 ma (3) 550 ? ? ? ? 550 550 mhz 1.5-v differential hstl class i (5) 4 ma 300 ? ? ? ? 300 300 mhz 6 ma 500 ? ? ? ? 500 500 mhz 8 ma 650 ? ? ? ? 650 650 mhz 10 ma 700 ? ? ? ? 700 700 mhz 12 ma (3) 700 ? ? ? ? 700 700 mhz table 4?35. hardcopy ii maximum output cloc k rate of hc210, hc220, HC230 and hc240 devices note (1) (part 4 of 5) i/o standard drive strength memory interface ioes high speed ioes general purpose ioes clk [0, 2, 8, 10] (2) clk [4..7, 12..15] pll_out unit bottom column right row
altera corporation 4?29 september 2008 maximum output clock rates 1.5-v differential hstl class ii (5) 16 ma 600 ? ? ? ? 600 600 mhz 18 ma 600 ? ? ? ? 600 600 mhz 20 ma (3) 650 ? ? ? ? 650 650 mhz notes to table 4?35 : (1) the toggle rate applies to 0 pf output load for all i/ o standards except for lvds an d hypertransport technology on row i/o pins. for lvds and hypertra nsport technology on row i/o pins, th e toggle rates apply to load from 0 to 5 pf. (2) clk [1, 3, 9, 11] and fpll_clk are dedicated input clocks, an d are excluded from this table. (3) this is the default setting in the quartus ? ii software if supported by the pin location. (4) the pci clamping diode is only suppo rted on the top and bottom i/o pins. (5) like stratix ii devices, differential hstl and sstl is supported only on the column clk , pll_out and memory interface dqs ioe pins. for hc210 and hc220, only the top column clock pins support differential hstl and sstl. table 4?35. hardcopy ii maximum output cloc k rate of hc210, hc220, HC230 and hc240 devices note (1) (part 5 of 5) i/o standard drive strength memory interface ioes high speed ioes general purpose ioes clk [0, 2, 8, 10] (2) clk [4..7, 12..15] pll_out unit bottom column right row table 4?36. hardcopy ii maximum out put clock rate for hc210w devices notes (1) , (6) (part 1 of 4) i/o standard drive strength memory interface ioes high speed ioes general purpose ioes clk [0, 2, 8, 10] (2) clk [4..7, 12..15] pll_out unit bottom column right row 3.3-v lvttl 4 ma 100 100 100 100 100 100 100 mhz 8 ma 170 170 170 170 170 170 170 mhz 12 ma 230 230 230 230 230 230 230 mhz 16 ma 240 ? ? ? ? 240 240 mhz 20 ma 280 ? ? ? ? 280 280 mhz 24 ma (3) 300 ? ? ? ? 300 300 mhz 3.3-v lvcmos 4 ma 175 175 175 175 175 175 175 mhz 8 ma 230 230 230 230 230 230 230 mhz 12 ma 260 ? ? ? ? 260 260 mhz 16 ma 270 ? ? ? ? 270 270 mhz 20 ma 290 ? ? ? ? 290 290 mhz 24 ma (3) 310 ? ? ? ? 310 310 mhz
4?30 altera corporation september 2008 hardcopy series handbook, volume 1 2.5-v lv t t l / lv c m o s 4 ma 136 136 136 136 136 136 136 mhz 8 ma 230 230 230 230 230 230 230 mhz 12 ma 370 370 370 370 370 370 370 mhz 16 ma (3) 405 ? ? ? ? 405 405 mhz 1.8-v lv t t l / lv c m o s 2ma77777777777777mhz 4 ma 150 150 150 150 150 150 150 mhz 6 ma 180 180 180 180 180 180 180 mhz 8 ma 200 200 200 200 200 200 200 mhz 10 ma 250 ? ? ? ? 250 250 mhz 12 ma (3) 290 ? ? ? ? 290 290 mhz 1.5-v lv t t l / lv c m o s 2ma60606060606060mhz 4 ma 110 110 110 110 110 110 110 mhz 6 ma 150 ? ? ? ? 150 150 mhz 8ma (3) 190 ? ? ? ? 190 190 mhz sstl2 class i 8 ma 210 ? ? ? ? 210 210 mhz 12 ma (3) 280 ? ? ? ? 280 280 mhz sstl2 class ii 16 ma 245 ? ? ? ? 245 245 mhz 20 ma 245 ? ? ? ? 245 245 mhz 24 ma (3) 280 ? ? ? ? 280 280 mhz sstl18 class i 4 ma 105 ? ? ? ? 105 105 mhz 6 ma 175 ? ? ? ? 175 175 mhz 8 ma 210 ? ? ? ? 210 210 mhz 10 ma 220 ? ? ? ? 220 220 mhz 12 ma (3) 230 ? ? ? ? 230 230 mhz sstl18 class ii 8 ma 140 ? ? ? ? 140 140 mhz 16 ma 220 ? ? ? ? 220 220 mhz 18 ma 220 ? ? ? ? 220 220 mhz 20 ma (3) 350 ? ? ? ? 350 350 mhz table 4?36. hardcopy ii maximum out put clock rate for hc210w devices notes (1) , (6) (part 2 of 4) i/o standard drive strength memory interface ioes high speed ioes general purpose ioes clk [0, 2, 8, 10] (2) clk [4..7, 12..15] pll_out unit bottom column right row
altera corporation 4?31 september 2008 maximum output clock rates 1.8-v hstl class i 4 ma 210 ? ? ? ? 210 210 mhz 6 ma 210 ? ? ? ? 210 210 mhz 8 ma 220 ? ? ? ? 220 220 mhz 10 ma 250 ? ? ? ? 250 250 mhz 12 ma (3) 270 ? ? ? ? 270 270 mhz 1.8-v hstl class ii 16 ma 190 ? ? ? ? 190 190 mhz 18 ma 200 ? ? ? ? 200 200 mhz 20 ma (3) 210 ? ? ? ? 210 210 mhz 1.5-v hstl class i 4 ma 150 ? ? ? ? 150 150 mhz 6 ma 160 ? ? ? ? 160 160 mhz 8 ma 170 ? ? ? ? 170 170 mhz 10 ma 180 ? ? ? ? 180 180 mhz 12 ma (3) 190 ? ? ? ? 190 190 mhz 1.5-v hstl class ii 16 ma 170 ? ? ? ? 170 170 mhz 18 ma 170 ? ? ? ? 170 170 mhz 20 ma (3) 170 ? ? ? ? 170 170 mhz pci (4) ? 315 ? 315 ? ? 315 315 mhz pci-x (4) ? 315 ? 315 ? ? 315 315 mhz lvds ? ? 320 ? ? ? ? 280 mhz hypertransport ? ? 320 ? ? ? ? ? mhz lvpecl ? ? ? ? ? ? ? 280 mhz differential sstl2 class i (5) 8 ma 210 ? ? ? ? 210 210 mhz 12 ma (3) 280 ? ? ? ? 280 280 mhz differential sstl2 class ii (5) 16 ma 245 ? ? ? ? 245 245 mhz 20 ma 245 ? ? ? ? 245 245 mhz 24 ma (3) 280 ? ? ? ? 280 280 mhz differential sstl18 class i (5) 4 ma 105 ? ? ? ? 105 105 mhz 6 ma 175 ? ? ? ? 175 175 mhz 8 ma 210 ? ? ? ? 210 210 mhz 10 ma 220 ? ? ? ? 220 220 mhz 12 ma (3) 230 ? ? ? ? 230 230 mhz table 4?36. hardcopy ii maximum out put clock rate for hc210w devices notes (1) , (6) (part 3 of 4) i/o standard drive strength memory interface ioes high speed ioes general purpose ioes clk [0, 2, 8, 10] (2) clk [4..7, 12..15] pll_out unit bottom column right row
4?32 altera corporation september 2008 hardcopy series handbook, volume 1 differential sstl18 class ii (5) 8 ma 140 ? ? ? ? 140 140 mhz 16 ma 220 ? ? ? ? 220 220 mhz 18 ma 220 ? ? ? ? 220 220 mhz 20 ma (3) 220 ? ? ? ? 220 220 mhz 1.8-v differential hstl class i (5) 4 ma 210 ? ? ? ? 210 210 mhz 6 ma 210 ? ? ? ? 210 210 mhz 8 ma 220 ? ? ? ? 220 220 mhz 10 ma 250 ? ? ? ? 250 250 mhz 12 ma (3) 270 ? ? ? ? 270 270 mhz 1.8-v differential hstl class ii (5) 16 ma 190 ? ? ? ? 190 190 mhz 18 ma 200 ? ? ? ? 200 200 mhz 20 ma (3) 210 ? ? ? ? 210 210 mhz 1.5-v differential hstl class i (5) 4 ma 150 ? ? ? ? 150 150 mhz 6 ma 160 ? ? ? ? 160 160 mhz 8 ma 170 ? ? ? ? 170 170 mhz 10 ma 180 ? ? ? ? 180 180 mhz 12 ma (3) 190 ? ? ? ? 190 190 mhz 1.5-v differential hstl class ii (5) 16 ma 170 ? ? ? ? 170 170 mhz 18 ma 170 ? ? ? ? 170 170 mhz 20 ma (3) 170 ? ? ? ? 170 170 mhz notes to table 4?36 : (1) the toggle rate applies to 0 pf output load for all i/o standards except for lvds and hypertransport technology on row i/o pins. for lvds and hypertranspo rt technology on row i/o pins, the to ggle rates apply to load from 0 to 5pf. (2) clk [1, 3, 9, 11] and fpll_clk are dedicated input clocks, and excluded from this table. (3) this is the default setting in the quartus ii software if supported by the pin location. (4) the pci clamping diode is only suppo rted on the top and bottom i/o pins. (5) like stratix ii devices, differential hstl and sstl is supported only on the column clk , pll_out and memory interface dqs ioe pins. for hc210 and hc220, only the top column clock pins support differential hstl and sstl. (6) these numbers are preliminary and pe nding further silico n characterization. table 4?36. hardcopy ii maximum out put clock rate for hc210w devices notes (1) , (6) (part 4 of 4) i/o standard drive strength memory interface ioes high speed ioes general purpose ioes clk [0, 2, 8, 10] (2) clk [4..7, 12..15] pll_out unit bottom column right row
altera corporation 4?33 september 2008 maximum output clock rates tables 4?37 and 4?38 show the maximum output toggle rates of hardcopy ii i/os using oct. table 4?37. hardcopy ii maximum output clock ra te for hc210, hc220, HC230 and hc240 devices (oct) note (1) (part 1 of 2) i/o standard drive strength memory interface ioes high speed ioes general purpose ioes clk [0, 2, 8, 10] (2) clk [4..7, 12..15] pll_out unit bottom column right row 3.3-v lvttl oct 50 400 400 400 400 400 400 400 mhz 2.5-v lvttl oct 50 350 350 350 350 350 350 350 mhz 1.8-v lvttl oct 50 550 550 550 550 550 550 550 mhz 3.3-v lvcmos oct 50 350 350 350 350 350 350 350 mhz 1.5-v lvcmos oct 50 450 450 450 450 450 450 450 mhz sstl-2 class i oct 50 500 ? ? ? ? 500 500 mhz sstl-2 class ii oct 25 550 ? ? ? ? 550 550 mhz sstl-18 class i oct 50 400 ? ? ? ? 400 400 mhz sstl-18 class ii oct 25 500 ? ? ? ? 500 500 mhz 1.5-v hstl class i oct 50 550 ? ? ? ? 550 550 mhz 1.8-v hstl class i oct 50 600 ? ? ? ? 600 600 mhz 1.8-v hstl class ii oct 50 500 ? ? ? ? 500 500 mhz differential sstl-2 class i (3) oct 50 500 ? ? ? ? 500 500 mhz differential sstl-2 class ii (3) oct 25 550 ? ? ? ? 550 550 mhz differential sstl-18 class i (3) oct 50 400 ? ? ? ? 400 400 mhz differential sstl-18 class ii (3) oct 25 500 ? ? ? ? 500 500 mhz 1.8-v differential hstl class i (3) oct 50 600 ? ? ? ? 600 600 mhz 1.8-v differential hstl class ii (3) oct 25 500 ? ? ? ? 500 500 mhz
4?34 altera corporation september 2008 hardcopy series handbook, volume 1 1.5-v differential hstl class i (3) oct 50 550 ? ? ? ? 550 550 mhz notes to table 4?37 : (1) the toggle rate applies to 0 pf output load for all i/o standards except for lvds and hypertransport technology on row i/o pins. for lvds and hypertra nsport technology on row i/o pins, the toggle rates apply to load from 0 to 5 pf. (2) clk [1, 3, 9, 11] and fpll_clk are dedicated input clocks, and excluded from this table. (3) like stratix ii devices, differential hstl and sstl is supported only on the column clk , pll_out and memory interface dqs ioe pins. for hc210 and hc220, only the top column clock pins support differential hstl and sstl. table 4?37. hardcopy ii maximum output clock ra te for hc210, hc220, HC230 and hc240 devices (oct) note (1) (part 2 of 2) i/o standard drive strength memory interface ioes high speed ioes general purpose ioes clk [0, 2, 8, 10] (2) clk [4..7, 12..15] pll_out unit bottom column right row table 4?38. hardcopy ii maximum output clock rate for hc210w using oct notes (1) , (4) (part 1 of 2) i/o standard drive strength memory interface ioes high speed ioes general purpose ioes clk [0, 2, 8, 10] (2) clk [4..7, 12..15] pll_out unit bottom column right row 3.3-v lvttl oct 50 280 280 280 280 280 280 280 mhz 2.5-v lvttl oct 50 245 245 245 245 245 245 245 mhz 1.8-v lvttl oct 50 290 290 290 290 290 290 290 mhz 3.3-v lvcmos oct 50 245 245 245 245 245 245 245 mhz 1.5-v lvcmos oct 50 190 190 190 190 190 190 190 mhz sstl-2 class i oct 50 280 ? ? ? ? 280 280 mhz sstl-2 class ii oct 25 280 ? ? ? ? 280 280 mhz sstl-18 class i oct 50 230 ? ? ? ? 230 230 mhz sstl-18 class ii oct 25 220 ? ? ? ? 220 220 mhz 1.5-v hstl class i oct 50 190 ? ? ? ? 190 190 mhz 1.8-v hstl class i oct 50 270 ? ? ? ? 270 270 mhz 1.8-v hstl class ii oct 50 210 ? ? ? ? 210 210 mhz
altera corporation 4?35 september 2008 highspeed i/o specifications highspeed i/o specifications table 4?39 provides high-speed timing specifications definitions. differential sstl-2 class i (3) oct 50 280 ? ? ? ? 280 280 mhz differential sstl-2 class ii (3) oct 25 280 ? ? ? ? 280 280 mhz differential sstl-18 class i (3) oct 50 230 ? ? ? ? 230 230 mhz differential sstl-18 class ii (3) oct 25 220 ? ? ? ? 220 220 mhz 1.8-v differential hstl class i (3) oct 50 270 ? ? ? ? 270 270 mhz 1.8-v differential hstl class ii (3) oct 25 210 ? ? ? ? 210 210 mhz 1.5-v differential hstl class i (3) oct 50 190 ? ? ? ? 190 190 mhz notes to table 4?38 : (1) the toggle rate applies to 0 pf output load for all i/ o standards except for lvds and hypertransport technology on row i/o pins. for lvds and hypertra nsport technology on row i/o pins, th e toggle rates apply to load from 0 to 5 pf. (2) clk [1, 3, 9, 11] and fpll_clk are dedicated input clocks, and excluded from this table. (3) like stratix ii devices, differential hstl and sstl is supported only on the column clk , pll_out and memory interface dqs ioe pins. for hc210 and hc220, only the top column clock pins support differential hstl and sstl. (4) these numbers are preliminary and pe nding further silico n characterization. table 4?38. hardcopy ii maximum output clock rate for hc210w using oct notes (1) , (4) (part 2 of 2) i/o standard drive strength memory interface ioes high speed ioes general purpose ioes clk [0, 2, 8, 10] (2) clk [4..7, 12..15] pll_out unit bottom column right row table 4?39. highspeed timing specifica tions and definitions (part 1 of 2) highspeed timing specifications definitions t c highspeed receiver/transmitter input and output clock period. f hsclk highspeed receiver/transmitter input and output clock frequency. j de-serialization factor (width of parallel data bus).
4?36 altera corporation september 2008 hardcopy series handbook, volume 1 table 4?40 shows the high-speed i/o timing specifications for hc210w f484 wirebond devices. w pll multiplication factor t rise low-to-high transmission time. t fall high-to-low transmission time. timing unit interval (tui) the timing budget allowed for skew, propagation delays, and data sampling window. (tui = 1/(receiver input clock frequency multiplication factor) = tc/w). f hsdr maximum/minimum lvds data transfer rate (f hsdr = 1/tui), non-dpa. f hsdrdpa maximum/minimum lvds data transfer rate (f hsdrdpa = 1/tui), dpa. channel-to-channel skew (tccs) the timing differen ce between the fastest and slowest output edges, including tco variation and clock sk ew. the clock is included in the tccs measurement. sampling window (sw) the period of time during which the data must be valid in order to capture it correctly. the setup and hold times determine the ideal strobe position within the sampling window. input jitter (peak-to-peak) peak-to- peak input jitter on highspeed plls. output jitter (peak-to-peak) peak-to- peak output jitter on highspeed plls. t duty duty cycle on highspeed transmitter output clock. t lock lock time for highspeed transmitter and receiver plls. table 4?39. highspeed timing specifica tions and definitions (part 2 of 2) highspeed timing specifications definitions table 4?40. hardcopy ii high-speed i/ o specifications for hc210w device notes (1) , (2) (part 1 of 2) symbol conditions min typ max unit f hsclk (clock frequency) f hsclk = f hsdr / w w = 2 to 32 (lvds, hypertransport technology) (3) 16 ? 320 mhz w = 1 (serdes bypass, lvds only) 16 ? 320 mhz w = 1 (serdes used, lvds only) 150 ? 320 mhz f hsdr (data rate) j = 4 to 10 (lvds, hypertransport technology) 150 ? 640 mbps j = 2 (lvds, hypertransport technology) (4) ? 640 mbps j = 1 t(lvds only) (4) ? 320 mbps f hsdrdpa (dpa data rate) j = 4 to 10 (lvds, hypertransport technology) 150 ? 640 mbps tccs all differential standards ? ? 240 ps sw all differential standards 400 ? ? ps output jitter ? ? ? (5) ps
altera corporation 4?37 september 2008 highspeed i/o specifications table 4?41 shows the high-speed i/o timing specifications for hc210, hc220, HC230 and hc240 hardcopy ii devices. output t rise all differential i/o standards ? ? (5) ps output t fall all differential i/o standards ? ? (5) ps t duty ???455055% dpa run length ? ? ? ? ? 6,400 ui dpa jitter tolerance (peak-to-peak) ??? (5) ?? ui dpa lock time standard training pattern transition density ? ? ? number of repetitions ?????? spi4 0000000000 1111111111 10% (5) ?? parallel rapid i/o 10010000 25% (5) ?? ? 10010000 50% (5) ?? miscellaneous 10101010 100% (5) ?? ? 10101010 ? (5) ?? notes to table 4?40 : (1) these numbers are preliminary and pe nding further silico n characterization. (2) when j = 4 to 10, the serdes block is used. when j = 1 or 2, the serdes block is bypassed. (3) the input clock frequency and the w factor must sa tisfy the following fast pll vco specification: 150 input clock frequency w 640. (4) the minimum specification is dependen t on the clock source (fast pll, enhanced pll, clock pin, and so on) and the clock routing resource (global, regional, or local) us ed. the i/o differential buffer and input register do not have a minimum toggle rate. (5) contact the altera applications group for more information. table 4?40. hardcopy ii high-speed i/ o specifications for hc210w device notes (1) , (2) (part 2 of 2) symbol conditions min typ max unit table 4?41. hardcopy ii high-speed i/o specifications for hc210, hc22 0, HC230 and hc240 devices note (1) (part 1 of 2) symbol conditions min typ max unit f hsclk (clock frequency) f hsclk = f hsdr / w w = 2 to 32 (lvds, hypertransport technology) (2) 16 ? 520 mhz w = 1 (serdes bypass, lvds only) 16 ? 500 mhz w = 1 (serdes used, lvds only) 150 ? 717 mhz
4?38 altera corporation september 2008 hardcopy series handbook, volume 1 f hsdr (data rate) j = 4 to 10 (lvds, hypertransport technology) 150 ? 1,040 mbps j = 2 (lvds, hypertransport technology) (3) ? 760 mbps j = 1 (lvds only) (3) ? 500 mbps f hsdrdpa (dpa data rate) j = 4 to 10 (lvds, hypertransport technology) 150 ? 1,040 mbps tccs all differential standards ? ? 200 ps sw all differential standards 330 ? ? ps output jitter ? ? ? 190 ps output t rise all differential i/o standards ? ? 160 ps output t fall all differential i/o standards ? ? 180 ps t duty ?455055% dpa run length ? ? ? 6,400 ui dpa jitter tolerance (peak-to-peak) ?0.44??ui dpa lock time standard training pattern transition density ? ? ? number of repetitions ?????? spi4 0000000000 1111111111 10% 256 ? ? parallel rapid i/o 10010000 25% 256 ? ? ? 10010000 50% 256 ? ? miscellaneous 10101010 100% 256 ? ? ? 10101010 ? 256 ? ? notes to table 4?41 : (1) when j = 4 to 10, the serdes block is used. when j = 1 or 2, the serdes block is bypassed. (2) the input clock frequency and the w factor must sa tisfy the following fast pll vco specification: 150 input clock frequency w 1,040. (3) the minimum specification is dependen t on the clock source (fast pll, enhanced pll, clock pin, and so on) and the clock routing resource (global, regional, or local) us ed. the i/o differential buffer and input register do not have a minimum toggle rate. table 4?41. hardcopy ii high-speed i/o specifications for hc210, hc22 0, HC230 and hc240 devices note (1) (part 2 of 2) symbol conditions min typ max unit
altera corporation 4?39 september 2008 pll timing specifications pll timing specifications tables 4?42 and 4?43 describe the hardcopy ii pll specifications when operating in both the commercial junction temperature range (0 to 85 c) and the industrial junction temperat ure range (?40 to 100 c), except for the clock switchover feature. like the stratix ii devices, the clock switchover feature is only suppo rted from the 0 to 100 c junction temperature range. table 4?42. hardcopy ii enhanced pll specifications (part 1 of 2) name description min typ max unit f in input clock frequency for hc210, hc220, HC230 and hc240 devices 2 ? 500 mhz input clock frequency for the hc210w device 2 ? 320 (1) mhz f inpfd input frequency to the pfd 2 ? 420 mhz f induty input clock duty cycle 40 ? 60 % f einduty external feedback input clock duty cycle 40 ? 60 % t injitter input or external feedback clock input jitter tolerance in terms of period jitter. bandwidth 0.85 mhz ?0.5 ? ns (pp) input or external feedback clock input jitter tolerance in terms of period jitter. bandwidth > 0.85 mhz ?1 ? ns (pp) t outjitter dedicated clock output period jitter for hc210, hc220, HC230 and hc240 devices ??250ps for 100 mhz outclk 25 mui for < 100 mhz outclk ps or mui dedicated clock output period jitter for hc210w device ??300ps for 100 mhz outclk 30 mui for < 100 mhz outclk ps or mui t fcomp external feedback compensation time ? ? 10 ns f out output frequency for internal global or regional clock 1.5 (2) ? 550 mhz t outduty duty cycle for external clock output (when set to 50%). 45 50 55 % f scanclk scanclk frequency ? ? 100 mhz t configepll time required to reconfigure scan chains for enhanced plls ? 174/f scanclk ?ns f out_ext pll external clock output frequency 1.5 (2) ? (1) mhz
4?40 altera corporation september 2008 hardcopy series handbook, volume 1 t lock time required for the pll to lock from the time it is enabled or the end of device configuration ?0.03 1 ms t dlock time required for the pll to lock dynamically after automatic clock switchover between two identical clock frequencies ?? 1 ms f switchover frequency range where the clock switchover performs properly 4 ? 500 mhz f clkw pll closed loop bandwidth 0.13 1.2 16.9 mhz f vco pll vco operating range for hc210, hc220, HC230 and hc240 devices 300 ? 1,040 mhz pll vco operating range for hc210w devices 300 ? 840 mhz f ss spread spectrum modulation frequency 100 ? 500 mhz % spread percent down spread for a given clock frequency 0.4 0.5 0.6 % t pll_pserr accuracy of pll phase shift ? ? 15 ps t areset minimum pulse width on areset signal. 10 (3) ??ns 500 (4) ??ns t areset_reconfig minimum pulse width on the areset signal when using pll reconfiguration. reset the pll after scan done goes high. 500 ? ? ns notes to table 4?42 : (1) limited by i/o f max . (2) if the counter cascading feature of the pll is used, there is no minimum output clock frequency. (3) applicable when the pll input clock has been running continuously for at least 10 s. (4) applicable when the pll input clock has stopped toggling or has been running continuously for less than 10 s. table 4?42. hardcopy ii enhanced pll specifications (part 2 of 2) name description min typ max unit
altera corporation 4?41 september 2008 pll timing specifications table 4?43. hardcopy ii fast p ll specifications (part 1 of 2) name description min typ max unit f in input clock frequency for hc210, hc220, HC230 and hc240 devices 16 ? 717 mhz input clock frequency for the hc210w device 16 ? 320 (1) mhz f inpfd input frequency to the pfd 16 ? 500 mhz f induty input clock duty cycle 40 ? 60 % t injitter input clock jitter tolerance in terms of period jitter. bandwidth 2mhz ?0.5?ns (pp) input clock jitter tolerance in terms of period jitter. bandwidth > 0.2 mhz ?1?ns (pp) f vco upper vco frequency range for hc210, hc220, HC230 and hc240 devices 300 ? 1,040 mhz upper vco frequency range for hc210w devices 300 ? 840 mhz lower vco frequency range for hc210, hc220, HC230 and hc240 devices 150 ? 520 mhz lower vco frequency range for hc210w device 150 ? 420 mhz f out pll output frequency to gclk or rclk 4.6875 ? 550 mhz pll output frequency to lvds or dpa clock for hc210, hc220, HC230 and hc240 devices 150 ? 1,040 mhz pll output frequency to lvds or dpa clock for hc210w devices 150 ? 840 mhz f out_io pll clock output frequency to regular i/o pin 4.6875 ? (1) mhz t configpll time required to reconfigure scan chains for fast plls ?75/f scanclk ?ns f clbw pll closed loop bandwidth 1.16 5 28 mhz t lock time required for the pll to lock from the time it is enabled or the end of the device configuration ?0.031ms t pll_pserr accuracy of pll phase shift ? ? 30 ps t areset minimum pulse width on areset signal. 10 ? ? ns
4?42 altera corporation september 2008 hardcopy series handbook, volume 1 external memory interface specifications table 4?44 summarizes the maximum clock ra te that hardcopy ii devices can support with exte rnal memory devices. t areset_reconfig minimum pulse width on the areset signal when using pll reconfiguration. reset the pll after scan done goes high. 500 ? ? ns note to table 4?43 : (1) limited by i/o f max . table 4?43. hardcopy ii fast p ll specifications (part 2 of 2) name description min typ max unit table 4?44. hardcopy ii maximum clock rate support for external memory interfaces note (1) memory standards hardcopy ii device unit wire bond package hc210w (2) flip chip package hc210 / hc220 / HC230 / hc240 (3) com (c) ind (i) com (c) ind (i) ddr 150 133 200 200 mhz ddr2 (7) 150 133 267 233 mhz qdrii (6) 150 133 250 233 (5) mhz rldramii (6) 150 133 250 (4) 233 (4) mhz notes to table 4?44 : (1) hardcopy ii devices do not support pll-based external memory interface except fo r sdr sdrams which do not require the dll. (2) hc210w supports memory inte rface on the top i/o banks. (3) hc210 and hc220 support memory interface on the top i/o banks. HC230 and hc240 support memory interface on the top and bottom i/o banks. (4) you will need to under-clock a 300 mhz memory device. (5) you will need to under-clock a 250 mhz memory device. (6) based on a ddio scheme with the 1.8-v hstl i/o standard. (7) based on the pll dedicated scheme. use the same f max specification for static-p hy and auto-phy since the write-side is limited by the new tds/th specification.
altera corporation 4?43 september 2008 external memory interface specifications tables 4?45 through 4?51 contain hardcopy ii device specifications for the dedicated circuitry used for in terfacing with external memory devices. table 4?46 lists the maximum delay in th e fast timing model for the hardcopy ii dqs delay buffer. multiply the number of delay buffers that you are using in the dqs logic block to get the maximum delay achievable in your sy stem. for example, if you implement a 90 phase shift at 200 mhz, you use three delay buffers in mode 2. the maximum achievable delay from the dqs bloc k is then 3 .416 ps = 1.248 ns. table 4?45. dll frequency range specifications frequency mode frequency range resolution (degrees) 0 100 to 175 30 1 150 to 230 22.5 2 200 to 310 30 3 240 to 350 36 table 4?46. dqs delay buffer maximum delay in fast timing model dll frequency mode maximum delay per delay buffer unit 0 0.833 ns 1, 2, 3 0.416 ns table 4?47. dqs period jitter speci fications for dll-delayed clock (tdqs_jitter) note (1) number of dqs delay buffer stages (2) commercial industrial unit 1 80 110 ps 2 110 130 ps 3 130 180 ps 4 160 210 ps notes to ta b l e 4 ? 4 7 : (1) peak-to-peak period jitter on the phase shifted dqs clock. (2) delay stages used for requested dqs ph ase shift are reported in your project?s compilation report in the quartus ii software.
4?44 altera corporation september 2008 hardcopy series handbook, volume 1 table 4?48. dqs phase jitt er specifications for dl l-delayed clock (tdqs phase_jitter) note (1) number of dqs delay buffer stages (2) dqs phase jitter unit 130ps 260ps 390ps 4 120 ps notes to ta b l e 4 ? 4 8 : (1) peak-to-peak phase jitter on the phase sh ifted dds clock (digital jitter is caused by dll tracking). (2) delay stages used for re quested dqs phase shift are reported in your project?s compilation report in the quartus ii software. table 4?49. dqs phase-shift error spec ifications for dll-delayed clock (tdqs_pserr) note (1) number of dqs delay buffer stages (2) ) hc210, hc220, HC230 hc240 unit 130ps 260ps 390ps 4 120 ps notes to ta b l e 4 ? 4 9 : (1) this error specification is the absolute maximum and minimum error. for example, skew on three delay buffer stage s with an hc240 device is 105 ps or 52.5ps. (2) delay stages used for re quested dqs phase shift are reported in your project?s compilation report in the quartus ii software.
altera corporation 4?45 september 2008 hot socketing hot socketing hardcopy ii devices offer hot socketing, which is also known as hot plug-in or hot swap, and power sequ encing support without the use of any external devices. you can insert or remove a hardcopy ii device in a system during system operation wi thout causing undesirable effects to the running system bus or the board that was inserted into the system. the hot socketing feature in hardcopy ii devices allow: the device can be driven before power-up without any damage to the device itself. i/o pins remain tri-stated during power-up, so they do no disrupt bus operation when hardcopy ii i /os are inserted in the system. signal pins do not drive the v ccio , v ccpd , or v ccint power supplies. external input signals to i/o pins of the device do not internally power the v ccio or v ccint power supplies of the device via internal paths within the device. table 4?50. dqs bus clock skew adder specifications (tdqs_clock_skew_adder) note (1) mode dqs clock skew adder unit 4 dq per dqs 40 ps 9 dq per dqs 70 ps 18 dq per dqs 75 ps 36 dq per dqs 95 ps note to table 4?50 : (1) this skew specification is the absolute maximum and minimum skew. for example, skew on a 4 dq group is 40 ps or 20 ps. table 4?51. dqs phase offset delay per stage note (1) hardcopy ii devices min max unit all 9 14 ps note to table 4?51 (1) the delay settings are linear. the valid se ttings for phase offset are -64 to +63 for frequency mode 0 and -32 to +31 for freq uency modes 1, 2, and 3. the typical value equals the average of the minimum and maximum values.
4?46 altera corporation september 2008 hardcopy series handbook, volume 1 in a hot socketing situation, a device?s output buffers are turned off during system power-up or power-down. to simplify board design, hardcopy ii devices support any power-up or power-down sequence (v ccio and v ccint ). for mixed-voltage envi ronments, you can drive signals into the device before or during power-up or power-down without damaging the device. you can power up or power down the v ccio and v ccint pins in any sequence. the power supply ramp rates can range from 100 ns to 100 ms. all vcc supplies must power down within 100 ms of each other to prevent the i/o pins from driving out. during hot socketing, the i/o pin capacitance is less than 15 pf and th e clock pin capacitance is less than 20 pf. the hot socketing dc specification is | i iopin | < 300 a. the hot socketing ac specification is | i iopin | < 8 ma for 10 ns or less. 1 the dc specification applies when all vcc supplies to the device are stable in the powered-up or powered-down conditions. the ac specification applies when the device is being powered up or powered do wn in any of the conditions mentioned above. electrostatic discharge electrostatic discharge (esd) protection is a design practice that is integrated in altera fpgas and structured asic devices. hardcopy ii devices are no exception, and they are designed with esd protection on all i/o and power pins.
altera corporation 4?47 september 2008 electrostatic discharge figure 4?3 shows a typical hardcopy ii cmos i/o buffer structure which will be used to explain esd protection. figure 4?3. transistor-level diagram of hardcopy ii device i/o buffers the cmos output drivers in the i/o pins intrinsically provide electrostatic discharge pr otection. there are two cases to consider for esd voltage strikes: positive voltag e zap and negative voltage zap. a positive esd voltage zap occurs when a positive voltage is present on an i/o pin due to an esd charge event. this can cause the n+ (drain)/psubstrate junction of th e n-channel drain to break down and the n+ (drain)/p-substrate/n+ (source) intrinsic bipolar transistor turns on to discharge esd curren t from i/o pin to gnd.
4?48 altera corporation september 2008 hardcopy series handbook, volume 1 the dashed line (see figure 4?4 ) shows the esd current discharge path during a positive esd zap. figure 4?4. esd protection during positive voltage zap when the i/o pin receives a negative esd zap at the pin that is less than -0.7 v (0.7 v is the voltage drop across a diode), the intrinsic p-substrate/n+ drain diode is forward biased. hence, the discharge esd current path is from gnd to the i/o pin, as shown in figure 4?5 . figure 4?5. esd protection during negative voltage zap
altera corporation 4?49 september 2008 document revision history f details of esd protection are also outlined in the hot-socketing and power-sequencing feature and testing for altera devices white paper located on the altera website at www.altera.com . f for information on esd results of altera products, please see the reliability report on the altera website at www.altera.com . document revision history table 4?52 shows the revision history for this chapter. table 4?52. document revision history date and document version changes made summary of changes september 2008, v3.3 updated chapter number and metadata. ? september 2007 v3.2 updated ta b l e 4 ? 3 3 and table 4?34 . updated drive strength value in ta b l e 4 ? 3 6 . changed f in and f inpfd from 4 to 2 mhz in table 4?42 . added industrial values to table 4?44 . minor updates to correct information in tables. june 2007 v3.1 changed v to v ih in table 4?16 updated data for v ih in table 4?17 added table 4?29 updated ta b l e 4 ? 4 4 ? december 2006 v3.0 major updates with new electrical characterization data updated data in table 4?1, table 4?3, table 4?4, table 4?5,table 4?10, table 4?12, table 4?13, table 4?19, table 4?20, table 4?27 to table 4?31. added table 4?11 and tables 4?36 to table 4?50. merged tables 4?27 to table 4?32 into new tables 4?32 to table 4?33. merged tables 4?33 to table 4?36 into new tables 4?34 to table 4?35. added revision history a major update to the chapter due to new electrical characterization data availability. october 2005, v2.1 updated graphics. ? may 2005, v2.0 updated various tables throughout chapter. ? january 2005 v1.0 added document to the hardcopy series handbook. ?
4?50 altera corporation september 2008 hardcopy series handbook, volume 1
altera corporation 5?1 september 2008 preliminary 5. quartus ii support for hardcopy ii devices hardcopy ii device support altera ? hardcopy ? ii devices feature 1.2-v, 90 nm process technology, and provide a structured asic alternative to increasingly expensive multi-million gate asic designs. the hardcopy ii design methodology offers a fast time-to-market schedu le, providing asic designers with a solution to long asic developm ent cycles. usin g the quartus ? ii software, you can leverage a stratix ? ii fpga as a prototype and seamlessly migrate your design to a hardcopy ii device for production. this document discusses the following topics: ?hardcopy ii development flow? on page 5?3 ?hardcopy ii device resource guide? on page 5?7 ?hardcopy ii recommended settings in the quartus ii software? on page 5?12 ?hardcopy ii utilities menu? on page 5?25 1 for more information about hardcopy ii, hardcopy stratix, and hardcopy apex? devices, refer to the respective device data sheets in the hardcopy series handbook . hardcopy ii design benefits designing with hardcopy ii structured asics offers substantial benefits over other structured asic offerings: prototyping using a stratix ii fpga for functional verification and system development reduces total project development time seamless migration from a stratix ii fpga prototype to a hardcopy ii device reduces time to market and risk unified design methodology fo r stratix ii fpga design and hardcopy ii design reduces th e need for asic development software low up-front development cost of hardcopy ii devices reduces the financial risk to your project h51022-2.5
5?2 altera corporation september 2008 hardcopy series handbook, volume 1 quartus ii features for hardcopy ii planning with the quartus ii software you can design a hardcopy ii device using a stratix ii device as a prototype. the quartus ii software contains the following expanded features fo r hardcopy ii device planning: hardcopy ii companion device assignment ?identifies compatible hardcopy ii devices for migration with the stratix ii device currently selected. 1 this feature constrains the pi ns of your stratix ii fpga prototype making it compatible with your hardcopy ii device. it also constrains the correct resources available for the hardcopy ii device making sure that your stratix ii fpga design does not become incompatible. in addition, you are still required to compile the design targeting the hardcopy ii device to ensure that the design fits, routes, and meets timing. hardcopy ii utilities ?the hardcopy ii utilities functions create or overwrites hardcopy ii companio n revisions, change revisions to use, and compare revisions for equivalency. hardcopy ii advisor ?the hardcopy ii advisor helps you follow the necessary steps to successfully submit a hardcopy ii design to altera?s hardcopy design center. 1 the hardcopy ii advisor is similar to the resource optimization advisor and timi ng optimization advisor. the hardcopy ii advisor provides guidelines you can follow during development, reporting the tasks completed as well as the tasks that remain to be completed during development hardcopy ii floorplan ?the quartus ii software can show a preliminary floorplan view of your hardcopy ii design?s fitter placement results. hardcopy ii design archiving ?the quartus ii software archives the hardcopy ii design project?s files needed to handoff the design to the hardcopy design center. 1 this feature is similar to the quartus ii software hardcopy files wizard used for hardcopy stratix and hardcopy apex families.
altera corporation 5?3 september 2008 hardcopy ii development flow hardcopy ii device preliminary timing ?the quartus ii software performs a timing analysis of hardcopy ii devices based on preliminary timing models and fitter placements . final timing results for hardcopy ii devices are provided by the hardcopy design center. hardcopy ii handoff report -?the quartus ii software generates a handoff report containing informat ion about the hardcopy ii design used by the hardcopy design center in the design review process. formal verification ?cadence encounter conformal software can now perform formal verification between the source rtl design files and post-compile gate level netl ist from a hardcopy ii design. hardcopy ii development flow in the quartus ii software, you have two methods for designing your stratix ii fpga and hardcopy ii companion device together in one quartus ii project. design the hardcopy ii device first, and create the stratix ii fpga companion device second and bu ild your prototype for in-system verification design the stratix ii fpga first and create a hardcopy ii companion device second both of these flows are illustrated at a high level in figure 5?1 . the added features in the hardcopy ii utilities menu assist you in completing your hardcopy ii design for submission to altera?s hardcopy design center for back-end implementation.
5?4 altera corporation september 2008 hardcopy series handbook, volume 1 figure 5?1. hardcopy ii flow in quartus ii software notes for figure 5?1 : (1) refer to figure 5?2 for an expanded description of this process. (2) refer to figure 5?3 for an expanded description of this process. designing the stratix ii fpga first the hardcopy ii development flow be ginning with the stratix ii fpga prototype is very similar to a traditio nal stratix ii fpga design flow, but requires a few additional tasks be performed to mi grate the design to the hardcopy ii companion device. to design your hardcopy ii device using the stratix ii fpga as a prototy pe, complete the following tasks: specify a hardcopy ii device for migration compile the stratix ii fpga design create and compile the hardcopy ii companion revision compare the hardcopy ii companion revision compilation to the stratix ii device compilation figure 5?2 provides an overview highlig hting the development process for designing with a stratix ii fpga first and creating a hardcopy ii companion device second. select stratix ii device & hardcopy ii companion device design stratix ii first complete stratix ii device first flow (1) select hardcopy ii device & stratix ii companion device design stratix ii second complete hardcopy ii device first flow (2) in-system verification of stratix ii fpga design compare stratix ii & hardcopy ii design revisions generate hardcopy ii archive prepare design hdl handoff design archive for back-end migration design stratix ii first? ye s n o
altera corporation 5?5 september 2008 hardcopy ii development flow figure 5?2. designing stratix ii device first flow prototype your hardcopy ii design by selecting and then compiling a stratix ii device in the quartus ii software. after you compile the stratix ii desi gn successfully, you can view the hardcopy ii device resource guide in the quartus ii software fitter report to evaluate which hardcopy ii devices meet your design?s resource requirements. when you are satisfied with the compilation results and the choice of stratix ii and hardcopy ii devices, on the assignments menu, click settings . in the category list, select device . in the device page, select a hardcopy ii companion device. review hardcopy ii advisor select stratix ii companion device apply design constraints compile stratix ii design compile hardcopy ii companion revision create or overwrite hardcopy ii companion revision fix violations any violations? any violations? stratix ii prototype device development phase hardcopy ii companion device development phase design submission & back-end implementation phase ye s ye s no no generate handoff report prepare stratix ii design archive project for handoff in-system verification fits in hardcopy ii device? compare stratix ii & hardcopy ii revisions select a larger hardcopy ii companion device?
5?6 altera corporation september 2008 hardcopy series handbook, volume 1 after you select your hardcopy ii companion device, do the following: review the hardcopy ii advisor for required and recommended tasks to perform enable design assistant to run during compilation add timing and loca tion assignments compile your stratix ii design create your hardcopy ii companion revision compile your design for the hardcopy ii companion device use the hardcopy ii utilities to compare the hardcopy ii companion device compilation wi th the stratix ii fpga revision generate a hardcopy ii handoff report using the hardcopy ii utilities generate a hardcopy ii handoff archive using the hardcopy ii utilities arrange for submission of your hardcopy ii handoff archive to altera?s hardcopy design center for back-end implementation f for more information about the overall design flow using the quartus ii software, refer to the introduction to quartus ii manual on the altera website at www.altera.com . designing the hardcopy ii device first the hardcopy ii family presents a ne w option in desi gning unavailable in previous hardcopy families. you can design your hardcopy ii device first and create your stratix ii fpga prototype second in the quartus ii software. this allows you to see your potential maximum performance in the hardcopy ii device immediately during development, and you can create a slower performing fpga prototype of the design for in-system verification. this design process is similar to the traditional hardcopy ii design flow where you build the fpga first, but instead, you merely change the starting device family. the remaining tasks to complete your design for both stratix ii and hardcopy ii devices roughly follow the same process ( figure 5?3 ). the hardcopy ii advisor adjusts its list of tasks based on which device family you start with, stratix ii or hardcopy ii, to help you complete the process seamlessly.
altera corporation 5?7 september 2008 hardcopy ii device resource guide figure 5?3. designing hardcopy ii device first flow hardcopy ii device resource guide the hardcopy ii device resource guide compares the resources required to successfully compile a design with the resources available in the various hardcopy ii devices. th e report rates each hardcopy ii device and each device resource for how well it fits the design. the quartus ii software generates the hardcopy ii device resource guide for all designs successfully compiled for stratix ii devices. this guide is found in the fitter folder of the compilation report. figure 5?4 shows an example of the hardcopy ii device resource guide. refer to table 5?1 for an explanation of the color codes in figure 5?4 . review hardcopy ii advisor select stratix ii companion device apply design constraints compile hardcopy ii design compile stratix ii companion revision in-system verification create or overwrite stratix ii companion revision compare hardcopy ii & stratix ii revisions fix violations any violations? any violations? hardcopy ii device development phase stratix ii companion device development phase design submission & back-end implementation phase ye s ye s no no generate handoff report prepare hardcopy ii design generate hardcopy ii archive for handoff
5?8 altera corporation september 2008 hardcopy series handbook, volume 1 figure 5?4. hardcopy ii device resource guide use this report to determine which hardcopy ii device is a potential candidate for migration of your stratix ii design. the hardcopy ii device package must be compatible with th e stratix ii device package. a logic resource usage greater than 100% or a ratio greater than 1/1 in any category indicates that the design does not fit in that particular hardcopy ii device.
altera corporation 5?9 september 2008 hardcopy ii device resource guide the hardcopy ii architecture consists of an array of fine-grained hcells, which are used to build logic equivalent to stratix ii adaptive logic modules (alms) and digital signal processing (dsp) blocks. the dsp blocks in hardcopy ii devices match the functionality of the stratix ii dsp blocks, though timing of these blocks is diff erent than the fpga dsp blocks because they are construc ted of hcell macros. the m4k and m-ram memory blocks in hardcopy ii devices are equivalent to the stratix ii memory blocks. preliminary timing reports of the hardcopy ii device are available in the quartus ii software. final timing results of the hardcopy ii device are provided by the hardcopy design center after back-end migration is complete. f for more information about the hardco py ii device resources, refer to the introduction to hardcopy ii devices and the description, architecture and features chapters in the hardcopy ii device family data sheet in the hardcopy series handbook . table 5?1. hardcopy ii device resource guide color legend color package resource (1) device resources green (high) the design can migrate to the hardcopy ii package and the design has been fitted with target device migration enabled in the hardcopy ii companion device dialog box. the resource quantity is within the range of the hardcopy ii device and the design can likely migrate if all other resources also fit. you are still required to compile the hardcopy ii revision to make sure the design is able to route and migrate all other resources. orange (medium) the design can migrate to the hardcopy ii package. however, the design has not been fitted with target device migration enabled in the hardcopy ii companion device dialog box. the resource quantity is within the range of the hardcopy ii device. however, the resource is at risk of exceeding the range for the hardcopy ii package. if your target hardcopy ii device falls in this category, compile your design targeting the hardcopy ii device as soon as possible to check if the design fits and is able to route and migrate all other resources. you may need to migrate to a larger device. red (none) the design cannot migrate to the hardcopy ii package. the resource quantity exceeds the range of the hardcopy ii device. the design cannot migrate to this hardcopy ii device. note to ta b l e 5 ? 1 : (1) the package resource is constrained by the stratix ii fpga for which the design was compiled. only vertical migration devices within the same package are able to migrate to hardcopy ii devices.
5?10 altera corporation september 2008 hardcopy series handbook, volume 1 the report example in figure 5?4 shows the resource comparisons for a design compiled for a stratix i i ep2s130f1020 device. based on the report, the HC230f1020 device in the 1,020-pin fineline bga ? package is an appropriate hardcopy ii device to migrate to. if the HC230f1020 device is not specified as a migration target during the compilation, its package and migration compatibility is rated orange, or medium. the migration compatibilities of the other hardcopy ii devices are rated red, or none, because the package types are incompatible with the stratix ii device. the 1,020-pin fbga hc240 device is rated red because it is only compatible with the st ratix ii ep2s180f1020 device. figure 5?5 shows the report after the (unc hanged) design was recompiled with the hardcopy ii HC230f1020 device specified as a migration target. now the HC230f1020 device package and migration compatibility is rated green, or high. figure 5?5. hardcopy ii device resource guide with target migration enabled hardcopy ii companion device selection in the quartus ii software, you ca n select a hardcopy ii companion device to help structure your design for migration from a stratix ii device to a hardcopy ii device. to make your hardcopy ii companion device selection, on the assignments menu, click settings . in the settings dialog box in the category list, select device ( figure 5?6 ) and select your companion device from the available devices list. selecting a hardcopy ii companion device to go with your stratix ii prototype constrains the memory blocks, dsp blocks, and pin assignments, so that your stratix ii and hardcopy ii devices are migration-compatible. pin assignment s are constrained in the stratix ii design revision so that the hardcopy ii device selected is pin-compatible. the quartus ii software also constrains the stratix ii design revision so it does not use m512 memory blocks or exceed the number of m-ram blocks in the hardcopy ii companion device.
altera corporation 5?11 september 2008 hardcopy ii companion device selection figure 5?6. quartus ii settings dialog box you can also specify your hardcopy ii companion device using the following tool command language (tcl) command: set_global_assignment -name\ device_technology_migration_list < hardcopy ii device part number > for example, to select the HC230f1020 device as your hardcopy ii companion device for the ep2s130f1020c4 stratix ii fpga, the tcl command is: set_global_assignment -name\ device_technology_migration_list HC230f1020c
5?12 altera corporation september 2008 hardcopy series handbook, volume 1 hardcopy ii recommended settings in the quartus ii software the hardcopy ii development flow involves additional planning and preparation in the quartus ii software compared to a standard fpga design. this is because you are developing your design to be implemented in two devices: a prototyp e of your design in a stratix ii prototype fpga, and a companion revision in a hardcopy ii device for production. you need additional se ttings and constraints to make the stratix ii design compatible with th e hardcopy ii device and, in some cases, you must remove certain settings in the design. this section explains the additional se ttings and constraints necessary for your design to be successful in both stratix ii fpga and hardcopy ii structured asic devices. limit dsp and ram to hardcopy ii device resources on the assignments menu, click settings to view the settings dialog box. in the category list, select device . in the family list, select stratix ii . under companion device , limit dsp and ram to hardcopy ii device resources is turned on by default ( figure 5?7 ). this maintains compatibility between the stratix ii and hardcopy ii devices by ensuring your design does not use resources in the stratix ii device that are not available in the selected hardcopy ii device. 1 if you require additional memo ry blocks or dsp blocks for debugging purposes using signaltap ? ii, you can temporarily turn this setting off to compile an d verify your design in your test environment. however, your final stratix ii and hardcopy ii designs submitted to altera for back-end migration must be compiled wi th this setting turned on. figure 5?7. limit dsp and ram to hardc opy ii device resources check box enable design assistant to run during compile you must use the quartus ii design assistant to check all hardcopy series designs for design rule violatio ns before submitting the designs to the altera hardcopy design center. additionally, you must fix all critical and high-level errors. 1 altera recommends turning on the design assistant to run automatically during each compile, so that during development, you can see the violations you must fix.
altera corporation 5?13 september 2008 hardcopy ii recommended settings in the quartus ii software f for more information about the design assistant and the rules it uses, refer to the design guidelines for hardcopy series devices chapter of the hardcopy series handbook . to enable the design assistant to run during compilation, on the assignment menu, click settings . in the category list, select design assistant and turn on run design assistant during compilation ( figure 5?8 ) or by entering the following tcl command in the tcl console: set_global_assignment -name enable_drc_settings on figure 5?8. enabling de sign assistant timing settings beginning in quartus ii software version 7.1, timequest is the recommended timing analysis tool for all designs. classic timing analyzer is no longer supported and the hardcopy design center will not accept any designs which use classic timing analyzer for timing closure. if you are still using the classic timing analyzer, altera strongly recommends that you switch to timequest.
5?14 altera corporation september 2008 hardcopy series handbook, volume 1 1 for more information on how to switch to timequest, refer to the switching to the timequest timing analyzer chapter of the quartus ii handbook , volume 3, on the altera website at www.altera.com . when you specify the timequest analyzer as the timing an alysis tool, the timequest analyzer guide s the fitter and analyzes timing results after compilation. timequest the timequest timing analyzer is a po werful asic-style timing analysis tool that validates timing in your design by using an industry-standard constraint, analysis, and reportin g methodology. you can use the timequest timing analyzer?s gui or command-line interface to constrain, analyze, and report results for all timing paths in your design. before running the timequest timing analyzer, you must specify initial timing constraints that describe the clock characte ristics, timing exceptions, and signal transition arrival and required times. you can specify timing constraints in the syno psys design constraints (sdc) file format using the gui or command-li ne interface. the quartus ii fitter optimizes the placement of logic to meet your constraints. during timing analysis , the timequest timing analyzer analyzes the timing paths in the design, calculat es the propagation delay along each path, checks for timing co nstraint violations, and re ports timing results as slack in the report pane and in the console pane. if the timequest timing analyzer reports any timing violations, you can customize the reporting to view precise timing info rmation about specific paths, and then constrain those paths to correct th e violations. when your design is free of timing violations, you can be confident that the logic will operate as intended in the target device. the timequest timing analyzer is a co mplete static timing analysis tool that you can use as a sign-off tool fo r altera fpgas and structured asics. setting up the timequest timing analyzer if you want use timequest for timing analysis, from the assignments tab in the quartus ii software, click on timing analysis settings , and in the pop-up window, click the use timequest timing analyzer during compilation tab.
altera corporation 5?15 september 2008 hardcopy ii recommended settings in the quartus ii software use the following tcl command to use ti mequest as your timing analysis engine: set_global_assignment -name \ use_timequest_timing_analyzer on you can launch the timequest analyz er in one of the following modes: directly from the quartus ii software stand-alone mode command-line mode in order to perform a thorough static timing analysis, you would need to specify all the timing requirem ents. the most important timing requirements are clocks and generate d clocks, input and output delays, false paths and multi-cycle paths, minimum and maximum delays. in timequest, clock latency, and recovery and removal analysis are enabled by default. f for more information about timequest, refer to the quartus ii timequest timing analyzer chapter in volume 3 of the quartus ii handbook on the altera website at www.altera.com . constraints for clock effect characteristics the create_clock, create_generated_clock commands create ideal clocks and do not ac count for board effects. in order to account for clock effect characteristics, you can use the following commands: set_clock_latency set_clock_uncertainty 1 for more information about how to use these commands, refer to the quartus ii timequest timing analyzer chapter in volume 3 of the quartus ii handbook . beginning in quartus ii version 7. 1, you can use the new command d erive_clock_uncertainty to automatically derive the clock uncertainties. this command is useful when you are not sure what the clock uncertainties might be. the calc ulated clock uncertainty values are based on i/o buffer, static phase errors (spe) and jitter in the pll's, clock networks, and core noises.
5?16 altera corporation september 2008 hardcopy series handbook, volume 1 the derive_clock_uncertainty command applies inter-clock, intra-clock, and i/o interface uncert ainties. this command automatically calculates and applies setup and ho ld clock uncertainties for each clock-to-clock transfer found in your design. in order to get i/o interface uncertainty, you must create a virtual clock, then assign delays to the in put/output ports by using the set_input_delay and set_output_delay commands for that virtual clock. 1 these uncertainties are applied in addition to those you specified using the set_clock_uncertainty command. however, if a clock uncertaint y assignment for a source and destination pair was already defined, the new one will be ignored. in this case, you can use either the -overwrite command to overwrite the previo us clock uncertainty command or manually remove them by using the remove_clock_uncertainty command. the syntax for the derive_clock _uncertainty is as follows: derive_clock_uncertainty [-h | -help] [-long_help] [-dtw] [-overwrite] where the arguments are listed in table 5?2 : when the dtw option is used, a pllj_pllspe_info. txt file is generated. this file lists the name of the plls, as well as their jitter and spe values in the design. this text file can be used by hcii_dtw_cu_calculator. when this option is used, clock uncertaintie s are not calculated. f for more information on the derive_clock_uncertainty command, refer to the quartus ii timequest timing analyzer chapter in volume 3 of the quartus ii handbook . table 5?2. arguments for derive_clock_uncertainty option description -h | -help short help -long_help long help with examples and possible return values -dtw creates pllj_pllspe_info. txt file -overwrite overwrites previously per formed clock uncertainty assignments
altera corporation 5?17 september 2008 hardcopy ii recommended settings in the quartus ii software altera strongly recommends that you use the derive_clock_uncertainty command in the hardcopy ii revision. the hardcopy design center will not be accepting designs that do not have clock uncertainty constr aint by either using the derive_clock_uncertainty command or the hardcopy ii clock uncertainty calculator, and then using the set_clock_uncertainty command. for more information on how to use the hardcopy ii clock uncertainty calculator, refer to the hardcopy ii clock uncertainty user guide available on the altera website at www.altera.com . quartus ii software features supported for hardcopy ii designs the quartus ii software supports optimization features for hardcopy ii prototype development, including: physical synthesis optimization logiclock regions powerplay power analyzer incremental compilation (synthesis and fitter) maximum fan-out assignments physical synthesis optimization to enable physical synthesis opti mizations for the stratix ii fpga revision of the design, on the assignments menu, click settings . in the settings dialog box, in the category list, select fitter settings . these optimizations are migrated into the hardcopy ii companion revision for placement and timing closure. wh en designing with a hardcopy ii device first, physical synthesis op timizations can be enabled for the hardcopy ii device, and these post-fit optimizations are migrated to the stratix ii fpga revision. logiclock ? regions the use of logiclock regions in th e stratix ii fpga is supported for designs migrating to hardcopy ii. however, logiclock regions are not passed into the hardcopy ii companion revision. you can use logiclock in the hardcopy ii design but you must create new logiclock regions in the hardcopy ii companion revision. in addition, logiclock regions in hardcopy ii devi ces can not have their properties set to auto size . however, floating logicl ock regions are supported. hardcopy ii logiclock regions must be manually sized and placed in the floorplan. when logiclock regi ons are created in a hardcopy ii device, they start with width and height dimensions set to ( 1,1 ), and the origin coordinates for placement are at x1_y1 in the lower left corner of
5?18 altera corporation september 2008 hardcopy series handbook, volume 1 the floorplan. you must adjust the si ze and location of the logiclock regions you created in the hardcopy ii device before compiling the design. f for information about using lo giclock regions, refer to the quartus ii analyzing and op timizing design floorplan chapter in volume 2 of the quartus ii handbook . powerplay power analyzer you can perform power estimation and analysis of your hardcopy ii and stratix ii devices using the powerplay early power estimator. use the powerplay power analyzer for more accu rate estimation of your device?s power consumption. the powerplay early power estimator is available in the quartus ii software version 5.1 and later. the powerplay power analyzer supports hardcopy ii devices in version 6.0 and later of the quartus ii software. f for more information about using th e powerplay power analyzer, refer to the quartus ii powerplay power analysis chapter in volume 3 of the quartus ii handbook on the altera website at www.altera.com . incremental compilation the use of the quartus ii incremental compilation in the stratix ii fpga is supported when migrating a design to a hardcopy ii device. incremental compilation is supported in the stratix ii first design flow or hardcopy ii first design flow. to take advantage of quartus ii incr emental compilation, organize your design into logical and physical partitions for synthesis and fitting (or place-and-route). incremental compilation preserves the compilation results and performance of unchanged partitions in your design. this feature dramatically reduces your design iteration time by focusing new compilations only on changed design partitions. new compilation results are then merged with the previous compilation results from unchanged design partitions. you can also targ et optimization techniques, such as physical synthesis, to specific partitions while leaving other partitions untouched. in addition, be aware of the following guidelines: user partitions and synthesis results are migrated to a companion device. logiclock regions are suggested fo r user partitions, but are not migrated automatically.
altera corporation 5?19 september 2008 performing ecos with change manager and chip planner the first compilation after migratio n to a companion device requires a full compilation (all partitions are compiled), but subsequent compilations can be incremental if changes to the source rtl are not required. for example, pll phas e changes can be implemented incrementally if the blocks are partitioned. the entire design must be migrated between stratix ii and hardcopy ii companion devices. the quartus ii software does not support migration of partitions between companion devices. bottom-up quartus ii in cremental compilation is not supported for hardcopy ii devices. physical synthesis can be run on individual partitions within the originating device only. the resulting optimizations are preserved in the migration to the companion device. f for information about using quartus ii incremental compilation, refer to the quartus ii incremental compilation for hierarchical and team-based design chapter in volume 1 of the quartus ii handbook . maximum fanout assignments this feature is supported beginning in quartus ii 6.1. in order to meet timing, it may be necessary to limit the number of fanouts of a net in your design. you can limit the maximum fanout of a given net by using this feature. for example, you can use the following tcl command to enable the maximum fanout setting: set_instance_assignment -name max_fanout - to\ for example, if you want to limit the maximum fanout of net called "m3122_combout_1" to 25, the tcl command is as follows: set_instance_assignment -name max_fanout 25 -to\ m3122_combout_1 performing ecos with change manager and chip planner as designs grow larger and larger in density, the need to analyze the design for performance, routing congestion, logic placement, and executing engineering change orde rs (ecos) becomes critical. in addition to design an alysis, you can use various bottom-up and top-down flows to implement and ma nage the design. this becomes difficult to manage since ecos are often implemented as last minute changes to your design.
5?20 altera corporation september 2008 hardcopy series handbook, volume 1 with the altera ? chip planner tool, you can sh orten the design cycle time significantly. when changes are made to your design as ecos, you do not have to perform a full compilation in the quartus ii software. instead, you would make changes directly to the post place-and-route netlist, generate a new programming file, test the revised design by performing a gate-level simulation and timing an alysis, and proceed to verify the fix on the system (if you are using a strati x ii fpga as a prototype). once the fix has been verified on the stratix ii fpga, switch to the hardcopy ii revision, apply the same ecos, run th e timing analyzer and assembler, perform a revision compare and then run the hardcopy ii netlist writer for design submission. there are three scenarios from a migration point of view: there are changes which can map one-to-one (that is, the same change can be implemented on each architecture?stratix ii fpga and hardcopy ii). there are changes that must be implemented differently on the two architectures to achieve the same result. there are some changes that cannot be implemented on both architectures. the following sections outline the me thods for migrating each of these types of changes. migrating one-to-one changes one-to-one changes are implemented us ing identical commands in both architectures. in general, such change s include those that affect only i/o cells or pll cells. some examples of one-to-one changes are changes such as creating, deleting or moving pins, changing pin or pll properties, or changing pin connectivity (provided the source and destination of the connectivity changes are i/os or plls). these can be implemented identically on both architectures. if such changes are exported to tcl, a direct reapplication of the generated tcl script (with a minor text edit) on the companion revision should implement the appropriate changes as follows: export the changes from the change manager to tcl. open the generated tcl script, change the line "project_open < project > -revision < revision >" to refer to the appropriate companion revision. apply the tcl script to the companion revision.
altera corporation 5?21 september 2008 performing ecos with change manager and chip planner a partial list of examples of this type are as follows: i/o creation, dele tion, and moves i/o property changes (for exampl e, i/o standards, delay chain settings, etc.) pll property changes connectivity changes between non-lcell_comb atoms (for example, pll to i/o, dsp to i/o, etc.) migrating changes that must be implemented differently some changes must be implemented diff erently on the tw o architectures. changes affecting the logic of the de sign may fall into this category. examples are lutmask changes, lc_comb/hsadder creation and deletion, and connectivity changes not covered in the previous section. another example of this would be to have different pll settings for the stratix ii and the hardcopy ii revisions. f for more information about how to use different pll settings for the stratix ii and hardcopy ii devices, refer to an432: using different pll settings between stratix ii and hardcopy ii devices . table 5?3 summarizes suggested implem entation for various changes. table 5?3. implementation suggestions for various changes (part 1 of 2) change type suggested implementation lutmask changes because a single stratix ii atom may require multiple hardcopy ii atoms to implement, it may be necessary to change multiple hardcopy ii atoms to implement the change, including adding or modifying connectivity make/delete lc_comb if you are using a stratix ii lc_comb in extended mode (7-lut) or using a share chain, you must create multiple atoms to implement the same logic functions in hardcopy ii. additionally, the placement of the lc_comb cell has no meaning in the companion revision as the underlying resources are different.
5?22 altera corporation september 2008 hardcopy series handbook, volume 1 changes that cannot be migrated a small set of changes cannot be impl emented in the other architecture because they do not make sense in the other architecture. the best example of this occurs when moving logic in a design; because the logic fabric is different between the two ar chitectures, locations in stratix ii make no sense in hardcopy ii and vice versa. overall migration flow this section outlines the migration flow and the suggested procedure for implementing changes in both revisions to ensure a successful revision compare such that the design can be submitted to the hardcopy design center. preparing the revisions the general procedure for migrating changes between devices is the same, whether going from stratix ii to hardcopy ii or vice versa. the major steps are as follows: 1. compile the design on the initial device. 2. migrate the design from the initial device to the target device in the companion revision. 3. compile the companion revision. 4. perform a revision compare oper ation. the two revisions should pass the revision compare. make/delete lc_ff the basic creation and deletion is the same on both architectures. however, as with lc_comb creation and deletion, the location of an lc_ff in a hardcopy ii revision has no meaning in the stratix ii revision and vice versa. editing logic connectivity because a st ratix ii lcell_comb atom may have to be broken up into several hardcopy ii lcell_comb atoms, the source or destination ports for connectivity changes may need to be analyzed to properly implement the change in the companion revision. table 5?3. implementation suggestions for various changes (part 2 of 2) change type suggested implementation
altera corporation 5?23 september 2008 overall migration flow if testing identifies pr oblems requiring eco changes, equivalent changes can be applied to both stratix ii and hardcopy ii revisions, as described in the next section. applying eco changes the general flow for applying equiva lent changes in companion revisions is as follows: 1. make changes in one revision us ing the chip planner tools (chip planner, resource property edi tor, and change manager), then verify and export these changes. th e procedure for doing this is as follows: a. make changes using the chip planner tool. b. perform a netlist check using the check and save all netlist changes command. c. verify correctness using timing analysis, simulation, and prototyping (stratix ii only). if more changes are required, repeat steps a-b. d. export change records from the change manager to tcl scripts, or .csv or .txt file formats. this exported file is used to as sist in making the equivalent changes in the companion revision. 2. open the companion revision in the quartus ii software. 3. using the exported file, manual ly reapply the changes using the chip planner tool. as stated previously, some changes can be reapplied directly to the companion revision (either manu ally or by applying the tcl commands), while others require some modifications. 4. perform a revision compare oper ation. the revisions should now match once again. 5. verify the correctness of all ch anges (you may need to run timing analysis). 6. run the hardcopy ii assembler and the hardcopy ii netlist writer for design submission along with handoff files.
5?24 altera corporation september 2008 hardcopy series handbook, volume 1 the tcl command for running the hardcopy ii assembler is as follows: execute_module -tool asm -args "-- read_settings_files=\ off --write_settings_files=off" the tcl command for the hardcopy ii netlist writer is as follows: execute_module -tool cdb -args "-- generate_hardcopyii_files"\ f for more information about usin g chip planner, refer to the quartus ii engineering change manage ment with chip planner chapter in volume 3 of the quartus ii handbook at www.altera.com . formal verification of stratix ii and hardcopy ii revisions third-party formal verification software is available for your hardcopy ii design. cadence encounter conformal verification software is used for stratix ii and hardcopy ii families, as well as several other altera product families. to use the conformal software with the quartus ii software project for your stratix ii and hardcopy ii design revisions, you must enable the eda netlist writer. it is necessary to turn on the eda netlist writer so it can generate the necessary netlists an d command files needed to run the conformal software. to automatically run the eda netlist writer during the compile of your stratix ii and hardcopy ii design revisions, perform the following steps: 1. on the assignment menu, click eda tool settings . the settings dialog box displays. 2. in the eda tool settings list, select formal verification , and in the to o l n a m e list, select conformal lec . 3. compile your stratix ii and hardcopy ii design revisions, with both the eda tool settings and the conformal lec turned on so the eda netlist writer automatically runs. the quartus ii eda netlist writer prod uces one netlist for stratix ii when it is run on that revision, and genera tes a second netlist when it runs on the hardcopy ii revision. you can co mpare your stratix ii post-compile netlist to your rtl source code using the scripts generated by the eda netlist writer. similarly, you can compare your hardcopy ii post-compile netlist to your rtl source code with scripts provided by the eda netlist writer.
altera corporation 5?25 september 2008 hardcopy ii utilities menu f for more information about using the cadence encounter conformal verification software, refer to the cadence encounter conformal support chapter in volume 3 of the quartus ii handbook . hardcopy ii utilities menu the hardcopy ii utilities menu in the quartus ii software is shown figure 5?9 . to access this menu, on the project menu, click hardcopy ii utilities . this menu contains the main functions you use to develop your hardcopy ii design and stratix ii fpga prototype companion revision. from the hardcopy ii utilities menu, you can: create or update hardcopy ii companion revisions set which hardcopy ii companion revision is the current revision generate a hardcopy ii handof f report for design reviews archive hardcopy ii handoff files for submission to the hardcopy design center compare the companion revision s for functional equivalence track your design progress using the hardcopy ii advisor figure 5?9. hardcopy ii utilities menu
5?26 altera corporation september 2008 hardcopy series handbook, volume 1 each of the features within hardcopy ii utilities is summarized in table 5?4 . the process for using each of th ese features is explained in the following sections. companion revisions hardcopy ii designs follow a diff erent development flow in the quartus ii software compared with previous hardcopy families. you can create multiple revisions of your st ratix ii prototype design, but you can also create separate revisions of yo ur design for a hardcopy ii device. table 5?4. hardcopy ii utilities menu options menu description applicable design revision restrictions create/overwrite hardcopy ii companion revision create a new companion revision or update an existing companion revision for your stratix ii and hardcopy ii design. stratix ii prototype design and hardcopy ii companion revision must disable auto device selection must set a stratix ii device and a hardcopy ii companion device set current hardcopy ii companion revision specify which companion revision to associate with current design revision. stratix ii prototype design and hardcopy ii companion revision companion revision must already exist compare hardcopy ii companion revisions compares the stratix ii design revision with the hardcopy ii companion design revision and generates a report. stratix ii prototype design and hardcopy ii companion revision compilation of both revisions must be complete generate hardcopy ii handoff report generate a report containing important design information files and messages generated by the quartus ii compile stratix ii prototype design and hardcopy ii companion revision compilation of both revisions must be complete compare hardcopy ii companion revisions must have been executed archive hardcopy ii handoff files generate a quartus ii archive file specifically for submitting the design to the hardcopy design center. similar to the hardcopy files wizard for hardcopy stratix and apex. hardcopy ii companion revision compilation of both revisions must be completed compare hardcopy ii companion revisions must have been executed generate hardcopy handoff report must have been executed hardcopy ii advisor open an advisor, similar to the resource optimization advisor, helping you through the steps of creating a hardcopy ii project. stratix ii prototype design and hardcopy ii companion revision none
altera corporation 5?27 september 2008 hardcopy ii utilities menu the quartus ii software creates specific hardcopy ii design revisions of the project in conjunction to the regu lar project revision s. these parallel design revisions for hardcopy ii devices are called companion revisions. 1 although you can create multiple project revisions, altera recommends that you maintain only one stratix ii fpga revision once you have created the hardcopy ii companion revision. when you have successfully compile d your stratix ii prototype fpga, you can create a hardcopy ii compan ion revision of your design and proceed with compiling the hardcopy ii companion revision. to create a companion revision, on the project menu, point to hardcopy ii utilities and click create/overwrite hardcopy ii companion revision . use the dialog box to create a new companion revision or overwrite an existing companion revision ( figure 5?10 ). figure 5?10. create or overwrite hardcopy ii companion revision you can associate only one strati x ii revision to one hardcopy ii companion revision. if you created more than one revision or more than one companion revision, set the curr ent companion for the revision you are working on. on the project menu, point to hardcopy ii utilities and click set current hardcopy ii companion revision ( figure 5?11 ).
5?28 altera corporation september 2008 hardcopy series handbook, volume 1 figure 5?11. set current hardcopy ii companion revision compiling the hardcopy ii companion revision the quartus ii software allows you to compile your hardcopy ii design with preliminary timing informatio n. the timing constraints for the hardcopy ii companion revision can be the same as the stratix ii design used to create the revision. the quar tus ii software contains preliminary timing models for hardcopy ii devi ces and you can gauge how much performance improv ement you can achieve in the hardcopy ii device compared to the stratix ii fpga. altera verifies that the hardcopy ii companion device timing requirements are met in the hardcopy design center. after you create your hardcopy ii companion revision from your compiled stratix ii design, select the companion revision in the quartus ii software design revision drop-down box ( figure 5?12 ) or from the revisions list. compile the hardcopy ii companion revision. after the quartus ii software compiles your de sign, you can perform a comparison check of the hardcopy ii companion revision to the stratix ii prototype revision. figure 5?12. changing current revision
altera corporation 5?29 september 2008 hardcopy ii utilities menu comparing hardcopy ii and stratix ii companion revisions altera uses the companion revisions in a single quartus ii project to maintain the seamless migration of your design from a stratix ii fpga to a hardcopy ii structured asic. this methodology allows you to design with one set of register transfer le vel (rtl) code to be used in both stratix ii fpga and hardcopy ii structured asic, guaranteeing functional equivalency. when making changes to companio n revisions, use the compare hardcopy ii companion revisions feat ure to ensure that your stratix ii design matches your hardcopy ii design functionality and compilation settings. to compare companion revisi ons, on the project menu, point to hardcopy ii utilities and click compare hardcopy ii companion revisions . 1 you must perform this comparis on after both stratix ii and hardcopy ii designs are compiled in order to hand off the design to altera?s hardcopy design center the comparison revision summary is found in the compilation report and identifies where assignments were changed between revisions or if there is a change in the logic resource count due to different compilation settings. generate hardcopy ii handoff report in order to submit a design to th e hardcopy design center, you must generate a hardcopy ii handof f report providing important information about the desi gn that you want the hardcopy design center to review. to generate the hardcopy ii handoff report, you must: successfully compile both strati x ii and hardcopy ii revisions of your design successfully run the compare hardcopy ii companion revisions utility once you generate the hardcopy ii handoff report, you can archive the design using the archive hardcopy ii handoff files utility described in ?archive hardcopy ii handoff files? on page 5?29 . archive hardcopy ii handoff files the last step in the hardcopy ii de sign methodology is to archive the hardcopy ii project for submission to the hardcopy design center for back-end migration. the hardcopy ii archive utility creates a different quartus ii archive file than the st andard quartus ii project archive
5?30 altera corporation september 2008 hardcopy series handbook, volume 1 utility generates. this archive contai ns only the necessary data from the quartus ii project needed to implem ent the design in the hardcopy design center. in order to use the archive hardcopy ii handoff files utility, you must complete the following: compile both the stratix ii and hardcopy ii revisions of your design run the compare hardcopy ii revisions utility generate the hardcopy ii handoff report to select this option, on the projec t menu, point to hardcopy ii utilities and click archive hardcopy ii handoff file utility. hardcopy ii advisor the hardcopy ii advisor provides the li st of tasks you should follow to develop your stratix ii prototype an d your hardcopy ii design. to run the hardcopy ii advisor, on the project menu, point to hardcopy ii utilities and click hardcopy ii advisor . the following list highlights the checkpoints that the hardcopy ii advisor reviews. this list includes the major check points in the design process; it does not show every step in the process for completing your stratix ii and hardcopy ii designs: 1. select a stratix ii device. 2. select a hardcopy ii device. 3. turn on the design assistant . 4. set up timing constraints. 5. check for incompatible assignments. 6. compile and check the stratix ii design. 7. create or overwrite the companion revision. 8. compile and check the hardcopy ii companion results. 9. compare companion revisions. 10. generate a handoff report. 11. archive handoff files and send to altera.
altera corporation 5?31 september 2008 hardcopy ii utilities menu the hardcopy ii advisor shows the necessary steps that pertain to your current selected device. the advisor shows a slightly different view for a design with stratix ii selected as co mpared to a design with hardcopy ii selected. in the quartus ii software, you can st art designing with the hardcopy ii device selected first, and build a stratix ii companion revision second. when you use this approach, the hardcopy ii advisor task list adjusts automatically to guide you from hardcopy ii development through stratix ii fpga prototyping, then co mpletes the comparison archiving and handoff to altera. when your design uses the stratix ii fpga as your starting point, altera recommends following the advisor guidelines for your stratix ii fpga until you complete the prototype revision. when the stratix ii fpga design is complete, create and switch to your hardcopy ii companion revision and follow the advisor steps shown in that revision until you are finished with the hardcopy ii revision and are ready to submit the design to altera for back-end migration. each category in the hardcopy ii advisor list has an explanation of the recommended settings and constraints, as well as quick links to the features in the quartus ii software th at are needed for each section. the hardcopy ii advisor displays: a green check box when you have su ccessfully completed one of the steps a yellow caution sign for steps that must be completed before submitting your design to alte ra for hardcopy development an information callout for items you must verify 1 selecting an item within the hardcopy ii flow menu provides a description of the task and recommended action. the view in the hardcopy ii advisor differs depending on the device you select.
5?32 altera corporation september 2008 hardcopy series handbook, volume 1 figure 5?13 shows the hardcopy ii advisor with the stratix ii device selected. figure 5?13. hardcopy ii advisor with stratix ii selected figure 5?14 shows the hardcopy ii advisor with the hardcopy ii device selected. figure 5?14. hardcopy ii advisor with hardcopy ii device selected
altera corporation 5?33 september 2008 hardcopy ii utilities menu hardcopy ii floorplan view the quartus ii software displays the preliminary timing closure floorplan and placement of your ha rdcopy ii companion revision. this floorplan shows the preliminary plac ement and connectivity of all i/o pins, plls, memory blocks, hcell macros, and dsp hcell macros. congestion mapping of routing conne ctions can be viewed using the layers setting dialog box (in the view menu) settings. this is useful in analyzing densely packed areas of your floorplan that could be reducing the peak performance of your desi gn. the hardcopy design center verifies final hcell macro timing and placement to guarantee timing closure is achieved. figure 5?15 shows an example of the HC230f1020 device floorplan. figure 5?15. HC230f1020 device floorplan in this small example design, the logi c is placed near the bottom edge. you can see the placement of a dsp block constructed of hcell macros, various logic hcell macros, and an m4k memory block. a labeled close-up view of this region is shown in figure 5?16 .
5?34 altera corporation september 2008 hardcopy series handbook, volume 1 figure 5?16. close-up view of floorplan the hardcopy design center perf orms final placement and timing closure on your hardcopy ii design based on the ti ming constraints provided in the stratix ii design. f for more information about the hardcopy design center?s process, refer to the back-end design flow fo r hardcopy series devices chapter in volume 1 of the hardcopy series de vice handbook . conclusion you can use the quartus ii software to design hardcopy ii devices and to develop prototypes using stratix ii fpgas. this is done using the standard fpga development process with the addition of the hardcopy ii device resource guide, hardcopy ii companion devices assignment hardcopy ii utilities, and the hardcopy ii advisor. the addition of the hardcopy ii advisor to the quartus ii software provides an instrumental development guide for you to complete your hardcopy ii and stratix ii device designs. the hardcopy ii utilities included in the quartus ii software provide you with the tools necessary to complete your stratix ii fpga prototype and hardcopy ii structured asic design. the addition of the hardcopy ii companion revisions feature to the process allows for rapi d development and verification that your hardcopy ii design is function ally equivalent to your stratix ii fpga prototype.
altera corporation 5?35 september 2008 document revision history document revision history table 5?5 shows the revision history for this chapter. table 5?5. document revision history date and document version changes made summary of changes september 2008, v2.5 updated chapter number and metadata. ? june 2007 v2.4 updated with the current quartus ii software version 7.1 information. ? december 2006 v2.3 minor updates for the quartus ii software version 6.1.0 added ?performing ecos with change manager and chip planner? and ?overall migration flow? sections. updated ?quartus ii software features supported for hardcopy ii designs? section. a medium update to the chapter, due to changes in the quartus ii software version 6.1 release; most changes were in the ?performing ecos with change manager and chip planner? and ?overall migration flow? sections. may 2006, v2.2 added information on support for hardcopy ii devices in version 6.0 of the quartus ii software. ? march 2006 formerly chapter 18; no content change. ? october 2005 v2.1 moved chapter 17 quartus ii support for hardcopy ii devices to chapter 18 in hardcopy series device handbook 3.2. updated graphics. updated technical content for quartus ii 5.1 support of hardcopy ii devices. ? may 2005 v2.0 added information on support for hardcopy ii devices in version 5.0 of the quartus ii software. ? january 2005 v1.0 added document to the hardcopy series handbook .?
5?36 altera corporation september 2008 hardcopy series handbook, volume 1
altera corporation 6?1 september 2008 6. script-based design for hardcopy ii devices introduction the quartus ? ii software includes a set of command-line executables, many of which support an interactive tcl shell. using the tcl shell, you can perform fpga or hardcopy ? design operations without using the quartus ? ii window-based gui. this chapter provides an introduction to tcl operations for script-based hardcopy ii design using the interactive tcl shell. topics covered in this chapter include: overview of tcl scripting features in the quartus ii software hardcopy ii design flow applying location an d timing constraints synthesis, place and route for ha rdcopy ii designs, and stratix ? ii prototypes design verificati on and analysis tcl support in the quartus ii software the quartus ii software provides different ways to execute tcl commands and scripts, including: a tcl console window a tcl scripts dialogue box command-line processing an interactive tcl shell the tcl console window and tc l s c r i p t s dialogue box both run within the quartus ii gui and are not described he re. instead, this chapter focuses on the interactive tcl shell that you can use with the quartus ii command-line executables. f for more information about command-line processing and the use of quartus ii command-line executables in batchfiles, makefiles, and scripts, refer to the command-line scripting chapter in volume 2 of the quartus ii handbook . f for more information on the quartu s ii tcl implementation, refer to the tcl reference manual and the tcl scripting chapter of the quartus ii handbook . h51025-1.3
6?2 altera corporation september 2008 hardcopy series handbook, volume 1 interactive tcl shell a number of the quartus ii executables can be run with an interactive tcl shell as the user interface. thes e executables are identified in table 6?1 . the interactive tcl shell supports tcl version 8.4. table 6?1. quartus ii command-line execut ables with interactive tcl support executable name description quartus_sh a basic tcl interpreter shell. supports assi gnment specification, compile operations, and native operating system commands. for more information, refer to quartus_sh in the command-line executables section of the quartus ii scripting reference manual . quartus_sta the quartus ii timequest timing analyzer engine supports building the timing graph for the design and timing analysis tcl commands. for more information, refer to quartus_sta in the command-line executables section of the quartus ii scripting reference manual. quartus_tan the quartus ii classic timing analyzer engine supports building the timing graph for the design and timing analysis tcl commands. for more information, refer to quartus_tan in the command-line executables section of the quartus ii scripting reference manual . quartus_cdb the quartus ii database interface executable. supports operations related to the design database such as logiclock, back-annotati on, and fpga-hardcopy comparison for hardcopy ii designs. for more information, refer to quartus_cdb in the command- line executables section of the quartus ii scripting reference manual . quartus_sim the quartus ii simulator. for more information, refer to quartus_sim in the command-line executables section of the quartus ii scripting reference manual .
altera corporation 6?3 september 2008 tcl support in the quartus ii software the interactive tcl shell for command-line executables is invoked using the -s command-line switch. for example, to run the basic quartus shell, type quartus_sh -s at the command prompt: % quartus_sh -s info: *********************************************************************** info: running quartus ii shell info: *********************************************************************** info: the quartus ii shell supports all tcl commands in addition info: to quartus ii tcl commands. all unrecognized commands are info: assumed to be external and are run using tcl's "exec" info: command. info: - type "exit" to exit. info: - type "help" to view a list of quartus ii tcl packages. info: - type "help -pkg " to view a list of tcl commands info: available for the specified quartus ii tcl package. info: - type "help -tcl" to get an overview on quartus ii tcl usages. info: *********************************************************************** tcl> the quartus ii tcl implementation provides custom tcl procedures to perform quartus ii operations. these procedures are organized into tcl packages based on their functionality. table 6?2 lists these tcl packages and their availability. some packages are loaded by default when the executable is invoked. others must be explicitly loaded before their tcl procedures are used. to load a particular package, use the load_package tcl procedure. for example, to load the flow package in the quartus_sh shell, the following tc l statement is executed: tcl> load_package flow 1 it is important to note that no t all executables support all tcl packages. table 6?2. tcl package support in quartus ii executables (part 1 of 2) executable name supported tcl package loaded by default? quartus_sta device loaded misc loaded flow not loaded project loaded report loaded sdc loaded sta loaded
6?4 altera corporation september 2008 hardcopy series handbook, volume 1 a brief description of each of the tcl packages referenced in table 6?2 is given in table 6?3 . f to find out which tcl packages are loaded, use the command quartus_??? --tcl_eval help. for example: quartus_sta --tcl_eval help. quartus_sh device loaded flow not loaded misc loaded project loaded report not loaded quartus_tan advanced_timing not loaded device not loaded flow not loaded logiclock not loaded misc loaded project loaded report not loaded timing loaded timing_report not loaded quartus_cdb backannotate not loaded chip_editor not loaded device loaded flow not loaded logiclock not loaded misc loaded project loaded report not loaded quartus_sim device loaded flow not loaded misc loaded project loaded report loaded simulator loaded table 6?2. tcl package support in quartus ii executables (part 2 of 2) executable name supported tcl package loaded by default?
altera corporation 6?5 september 2008 tcl support in the quartus ii software the quartus ii command-line executables and tcl shells are supported on all quartus ii operating systems, including micr osoft windows, linux, and unix platforms. f for more information on quartus ii tc l packages and their available tcl procedures, refer to the tcl packages and commands chapter in the quartus ii scripting reference manual . command-line processing in addition to the interactive tcl shell, the quartus ii command-line executables support command-line swit ches for executing tcl scripts and commands. when used with these switches, a command-line executable quits when complete. the command-line executables also provide switches for performing specific qu artus ii operations. for example, the following c-shell script takes as its argument the top-level design file and entity name and runs it through th e entire hardcopy ii design flow. !#/bin/csh quartus_sh --flow compile %1 quartus_cdb %1 --create_companion=%1_hcii quartus_sh --flow compile %1 -c %1_hcii quartus_cdb --compare=%1_hcii %1 -c %1 table 6?3. quartus ii tcl package descriptions tcl package description advanced_timing traverse the timing netlist and get information about timing modes. backannotate back annotate assignments. chip_editor identify and modify resource us age and routing with the chip editor. database_manager manage version-comparable database files. device get device and family information from the device database. flow compile a project, run command-line executables and other common flows. logiclock create and manage logiclock regions. misc perform miscellaneous tasks. project create and manage projec ts and revisions and make any project assignments including timing assignments. report get information from report tables and create custom reports. simulator configure and perform simulations. stp operate the signaltap ? ii analyzer. timing annotate timing netlist with delay information, compute and report timing paths. timing_report list timing paths.
6?6 altera corporation september 2008 hardcopy series handbook, volume 1 this example shows what is, perhap s, the simplest way to execute the hardcopy ii design flow. if you have developed and applied the design i/o, location and timing constraints for the project, these constraints are included during script execution. f for more information on the quartu s ii executables and command-line options, refer to the command-line executables chapter in the quartus ii scripting reference manual and the command-line scripting section in volume 2 of the quartus ii handbook . the hardcopy ii design flow the quartus ii software supports both hardcopy ii first and stratix ii first design flows. the stratix ii fi rst flow involves the following: compiling for the stratix ii fpga prototype verifying the stratix ii fpga prototype migrating the prototype design to a hardcopy ii design compiling the hardcopy ii design transferring your hardcopy ii files to the altera ? design center the hardcopy ii first flow is simila r, but starts with compiling the hardcopy ii target device. once the hardcopy ii compile completes successfully, the design is migrated to the stratix ii target. the hardcopy ii design flow in th e quartus ii software is shown in figure 6?1 . to begin a design, create a new project and revision for the stratix ii fpga prototype. apply quartus ii settings together with i/o assignments and timing constraints. compile the stratix ii prototype revision (synthesis, plac e and route, and assembly) to produce a complete layout, with timing closure and free from errors. you can now perform any additional functional and timing verificati on necessary and then implement and verify the prototype in hardware. once the fpga prototype is verified , you can compile the hardcopy ii design. begin by creating a hardcopy ii companion revision for the fpga prototype: 1. create a hardcopy ii companion revision for the fpga prototype. all design settings and constraints are automatically migrated to the new companion revision. 2. compile the hardcopy ii revision. as the compile runs, the design assistant checks for errors. wh en the compile completes, you should correct errors and resolve failures that appear in the quartus ii reports.
altera corporation 6?7 september 2008 the hardcopy ii design flow 3. run the hardcopy ii companion revision comparison tool to compare the hardcopy ii design against the fpga prototype. the comparison tool checks for structural equivalency and consistency between the two revisions. 4. if there are no mismatches, you can prepare the hardcopy ii design files for transfer to the altera design center. 1 in addition to design verification in the quartus ii software, the flow can generate files required to perform static timing analysis (sta) in synopsys? primetime. figure 6?1. the hardcopy ii design flow create a new project make global assignments make location assignments make timing assignments prototype stratix ii design hardcopy ii design source .v, .vhd, .tdf .edf, .bdf design files verify the stratix ii prototype compile stratix ii prototype compilation report files timing constraint tcl files compile hardcopy ii design create hardcopy ii companion revision verify hardcopy ii design hand-off to the altera design center hardcopy ii archive compare design report file signal-pin assignment tcl files compilation report files
6?8 altera corporation september 2008 hardcopy series handbook, volume 1 the design flow of figure 6?1 begins with a stratix ii fpga prototype design and migrates this design to a hardcopy ii device target, or begins with a hardcopy ii target and migrates this design to a stratix ii target for fpga prototyping. the design fl ow for both cases is shown in figure 6?1 . f for more information on the hardco py ii design flow and alternative methods to complete hardcopy ii de signs using the quartus ii gui, refer to the quartus ii support for hardcopy ii devices chapter in the quartus ii handbook or the hardcopy ii design considerations chapter in volume 1 of the hardcopy series handbook . the following sections describe ea ch step of the flow shown in figure 6?1 and explains how each step is completed using the interactive tcl shell. creating a new project both fpga and hardcopy design in the quartus ii software revolve around the use of projects. you must create a project before you begin working with a new design. a project includes source design files (rtl and schematics), quartus ii tool settin gs, and a set of pin locations and timing constraints. al though a project can contain many different revisions for a design, each revision can have a unique set of design constraints, target device settings, and quartus ii software settings. you must explicitly open a project before you can perform other operations on the project. you must close the current project to switch to a different project or revision. this section details the different operations relating to project management using tcl commands. creating a stratix ii prototype project to create a new stratix ii prototype project, use the project_new tc l command. the syntax for this command is: tcl> project_new [-family < family >] [-overwrite] \ [-part < part >] [-revision < revision_name >] \ < project_name > the only required argument for th is command is the project name, < project name >, although the target device family, part code, and revision name can be specified at this time also. by default, the revision name is the same as the project name. the device family and part code can be set later using the set_global_assignment command. for example, to create
altera corporation 6?9 september 2008 creating a new project a project called demo_design with the default revision name of demo_design and an unspecified target device family or part, the following tcl command is executed: tcl> project_new demo_design creating a new project creates a quartus settings file (qsf) and a quartus ii project file (qpf) in the cu rrent directory. in addition, a db subdirectory is created that is used to store quartus ii database files. in the case of the demo_design project example, the following files are created in the project directory: demo_design.qpf demo_design.qsf db/ demo_design.db_info opening a project the project created automatically opens when you use the project_new command. in future quartus ii sessions , or if you close the project, you must open the project with the tcl command: project_open . the syntax for the project_open command is: tcl> project_open [-current_revision] \ [-revision ] for example, to open the de fault revision of project demo_design , execute the following tcl command: tcl> project_open demo_design 1 it is a good practice to have consistent names for the stratix ii and hardcopy ii revisions of your project. this makes it easy to identify which revision is whic h. for example, naming your revisions projectname_fpga and projectname_hcii would help you easily identify which revision is the stratix ii revision, and which is the hardcopy ii revision. closing a project before ending a quartus ii project sessio n, it is good prac tice to close the quartus ii project using the project_close command. this ensures that any changes you have made to your project are written to the quartus ii qsf file. the syntax for the project_close command is: tcl> project_close [-dont_export_assignments]
6?10 altera corporation september 2008 hardcopy series handbook, volume 1 new project example script the following script shows the use of tcl commands for opening and closing a project called demo_design with the revision name, demo_design_fpga . if the project does not alre ady exist, it is created. this script makes use of the project_exists and project_open tc l commands. ## example tcl script for opening and closing a project ## open project demo_design. if the project does not already ## exist, create it if [is_project_open] project_close if [project_exists demo_design] { project_open demo_design -revision demo_design_fpga } else { project_new demo_design -revision demo_design_fpga } ## include other tcl commands here ? ## close project demo_design and write any changes to settings to ## demo_design.qsf project_close ## end of script f for more information on these and other useful project-related commands, refer to the project section in the tcl packages and commands chapter in the quartus ii scripting reference manual .
altera corporation 6?11 september 2008 making global assignments making global assignments initializing a hardcopy ii design for a hardcopy ii design, the followin g key operations are required after a quartus ii project is created: specify design source files (verilog, vhdl, ahdl, edif, and bdf files) specify the stratix ii prototype target family and device name specify the hardcopy ii companion revision and migration device enable the design assistant make recommended hardcopy ii sp ecific quartus ii tool settings in addition to these, other project se ttings affecting downstream tools, such as synthesis and place-and-ro ute, can be made at this time. the operations listed above are performed using the set_global_assignment command. the syntax for this command is: tcl> set_global_assignment [-comment] \ [-disable] [-entity < entity_name >] -name < name > \ [-remove] [-section_id < section_id >] < value > the most important parameters for the set_global_assignment command are < name > and < value >. the < name > argument specifies the quartus ii global variable to be set and < value > is the new value assigned to that variable. one of the steps in initializing a ha rdcopy ii design is to turn on the design assistant. when run in the gui, the design assistant provides a visual checklist for running both the stratix ii and hardcopy ii phases of the design. for first-time users, th is can provide a powerful guide for successfully completing your hardcopy ii project.
6?12 altera corporation september 2008 hardcopy series handbook, volume 1 the key global variables for a hardcopy ii project are listed in table 6?4 . table 6?4. key hardcopy ii design settings global variable name < name > value description < value > verilog_file verilog file name. vhdl_file vhdl file name. ahdl_file altera hdl file name. edif_file edif file name. bdf_file altera schematic file name. family device family name, for example, stratix ii. device prototype fpga target device name. top_level_entity top-level design entity or module name. device_technology_migration_list hardcopy ii target device name. companion_revision hardcopy ii design revision name. enable_drc_settings turn on the design assistant. use_timequest_timing_analyzer set timequest as the defau lt timing analyzer . sdc_file file of timequest constr aints . you only need the following settings when using classic timing analyzer. using classic timing analyzer is not recommended. report_io_paths_separately creates a separate report panel for input and output min and max timing results. flow_enable_timing_constraint_check timing constraints are checked for completeness (all clock domains constraints and minimum and maximum constraints are set for all i/o paths). do_combined_analysis timing analysis are run for fast and slow operating conditions and for best and wo rst-case timing analysis, respectively. ignore_clock_settings this must be turned off. enable_recovery_removal_analysis verify recovery and removal times on asynchronous control and reset signals. enable_clock_latency clock latency is included in timing analysis to asses clock-insertion timing and clock skew.
altera corporation 6?13 september 2008 making global assignments the device and device_technology_migration_list variables are the parts used for the stratix ii prototype design and the hardcopy ii design. the selected stratix ii prototype device must be compatible with the selected hardcopy ii device to make migration possible. valid pairings for these devices are listed in table 6?5 . for the device_technology_migration_list variable, the hardcopy ii part names listed in table 6?5 are used. for the device variables, the stratix ii part names include the speed grade for the part. the speed grade is a two character code indicating industrial (i) or commercial (c) and the speed indicator (number 3, 4, or 5). for example, a -4 commercial part is denoted using the two character speed grade c4 . the two-character speed grade is appended to the stratix ii part name to form the value string for the device variable. table 6?5. stratix ii prototype opti ons for hardcopy ii (part 1 of 2) hardcopy ii part stratix ii prototype part hc210f484c hc210w484c ep2s30f484c3 ep2s30f484c4 ep2s30f484c5 ep2s30f484i4 ep2s60f484c3 ep2s60f484c4 ep2s60f484c5 ep2s60f484i4 ep2s90h484c4 ep2s90h484c5 hc220f672c ep2s60f672c3 ep2s60f672c4 ep2s60f672c5 ep2s60f672i4 hc220f780c ep2s90f780c4 ep2s90f780c5 ep2s130f780c4 ep2s130f780c5
6?14 altera corporation september 2008 hardcopy series handbook, volume 1 the following two tcl commands demonstrate setting the device and device_technology_migration_list variables. tcl> set_global_assignment -name device ep2s90f1020c4 tcl> set_global_assignment -name \ device_technology_migration_list HC230f1020c HC230f1020c ep2s90f1020c3 ep2s90f1020c4 ep2s90f1020c5 ep2s90f1020i4 ep2s130f1020c3 ep2s130f1020c4 ep2s130f1020c5 ep2s130f1020i4 ep2s180f1020c3 ep2s180f1020c4 ep2s180f1020c5 ep2s180f1020i4 hc2401020c ep2s180f1020c3 ep2s180f1020c4 ep2s180f1020c5 ep2s180f1020i4 hc240f1508c ep2s180f1508c3 ep2s180f1508c4 ep2s180f1508c5 ep2s180f1508i4 table 6?5. stratix ii prototype opti ons for hardcopy ii (part 2 of 2) hardcopy ii part stratix ii prototype part
altera corporation 6?15 september 2008 making global assignments the design assistant you should turn on the design assistant at the beginning of the design process by turning on the enable_drc_settings global variable. tcl> set_global_assignment \ -name enable_drc_settings on the design assistant runs concurrent ly with every step of both the prototype stratix ii and hardcopy ii design flows. wh en the design assistant is turned on, the quartus ii software checks to ensure that the project fully complies with all hardcopy ii design rules and requirements. f for more information on the de sign assistant, refer to the design guidelines for hardcopy ii devices chapter in volume 1 of the hardcopy series handbook and the quartus support for hardcopy ii devices chapter in the quartus ii handbook .
6?16 altera corporation september 2008 hardcopy series handbook, volume 1 example tcl script for making global assignments the example tcl script below illustrates the application of global constraints for a hardcopy ii project. ## example global assignments script for a hardcopy ii design ## this script applies settings for a ep2s90 stratix ii ## prototype fpga target and a HC230 hardcopy ii target ## source design file settings ## =========================== set_global_assignment -name verilog_file demo_design.v set_global_assignment -name verilog_file example_ram.v ## stratix ii prototype fpga target settings ## ========================================= set_global_assignment -name family "stratix ii" set_global_assignment -name device ep2s90f1020c4 set_global_assignment -name top_level_entity demo_design ## hardcopy ii companion revision and target settings ## ================================================== set_global_assignment -name companion_revision_name \ demo_design_hardcopyii set_global_assignment -name device_technology_migration_list HC230f1020 ## design assistant assignments and settings required for hardcopy ii ##============================================================== set_global_assignment -name enable_drc_settings on set_global_assignment -name error_check_frequency_divisor 1 set_global_assignment -name report_io_paths_separately on ## the following assignments are classic timing analyzer only ## and are not used by timequest. ##=========================================================== set_global_assignment -name flow_enable_timing_constraint_check on set_global_assignment -name do_combined_analysis on set_global_assignment -name ignore_clock_settings off set_global_assignment -name enable_recovery_removal_analysis on set_global_assignment -name enable_clock_latency on ## end of script
altera corporation 6?17 september 2008 making global assignments making i/o assignments because of the complex rules gove rning the use of programmable i/o cells and their availability for specific pins and packages, altera highly recommends that i/o assignments are completed using the pin planning tool and the assignment editor in th e quartus ii gui. these tools ensure that all of the rules regarding each pin and i/o cell are applied correctly. the quartus ii gui can export a tcl sc ript containing al l i/o assignments and specifications. i/o assignments are described here for information only. f for more information on i/o locati on and type assignments using the quartus ii assignment editor an d pin planner tools, refer to the assignment editor chapter in volume 2 of the quartus ii handbook . in this section, i/o specification is considered in two parts: pin assignments i/o type assignments pin assignments design i/o signals are assigned to package balls using the set_location_assignment command. the syntax for this command is given below: tcl> set_location_assignment [-comment < comment >] \ [-disable] [-remove] -to < destination > < value > here, < destination > is the package ball name and < value > is the design i/o signal name. for bga and fbga pack ages, the ball name follows the form pin_ . for example, to assign design i/o signal data_out [ 15 ] to package ball al17: tcl> set_location_assignment -to pin_al17 data_out[15] setting i/o type and parameters for i/o type and parameter specification, the set_instance_assignment command is used. the syntax for this command is: tcl> set_instance_assignment [-comment ] \ [-disable] [-entity ] \ [-from < source >] -name < name > [-remove] \ [-section_id < section_id >] \ [-to < destination >] < value >
6?18 altera corporation september 2008 hardcopy series handbook, volume 1 the assignment name, < name >, should be set to io_standard to indicate that an i/o specification is being applied. the related i/o signal is specified as - to < destination >. the destination argument is a string providing details on the i/o type, such as levels and standards. table 6?6 lists the strings corresponding to the i/o standards supported in hardcopy ii devices. table 6?6. tcl i/o standard strings i/o type or < name > description lvttl lvttl i/o lvcmos lvcmos i/o ?3.3-v pci? 3.3-v pci i/o ?3.3-v pci-x? 3.3-v pci x i/o ?1.5 v? 1.5-v i/o ?1.8 v? 1.8-v i/o ?2.5 v? 2.5-v i/o ?1.5-v hstl class i? qdrii sram 1.5-v i/o ?1.5-v hstl class ii? qdrii sram 1.5-v i/o ?1.8-v hstl class i? qdrii sram/rldram ii 1.8-v i/o ?1.8-v hstl class ii? qdrii sram/rldram ii 1.8-v i/o ?differential 1.5-v hstl class i? memory clock interface ?differential 1.5-v hstl class ii? memory clock interface ?differential 1.8-v hstl class i? memory clock interface ?differential 1.8-v hstl class ii? memory clock interface ?differential 1.8-v sstl class i? ddr2 sdram ?differential 1.8-v sstl class ii? ddr2 sdram ?differential sstl-2? ddr sdram ?differential 2.5-v sstl class ii? ddr sdram ?sstl-18 class i? ddr2 sdram ?sstl-18 class ii? ddr2 sdram ?sstl-2 class i? ddr sdram ?sstl-2 class ii? ddr sdram lvds 2.5-v differential signaling hypertransport 2.5-v differential signaling lvpcl differential
altera corporation 6?19 september 2008 making global assignments you can specify a number of other i/o parameters by using the set_instance_assignment command. some of the more common parameters are listed in table 6?7 . f for more information on i/o availabi lity in hardcopy ii devices, refer to the i/o structures and features section in volume 1 of the hardcopy series handbook . table 6?7. tcl common i/o parameter settings < name > setting < value > setting description weak_pull_up_resistor on implement a weak pull-up resistor on the pin. output_pin_load integer capacitive load for an output or bidirectional pin. units of pf. fast_output_register on implements a fast output register in the i/o cell or adjacent lab. fast_output_enable_register on implement a fast output enable register in the i/o cell or/and adjacent lab. fast_input_register on implements a fast input register in the i/o cell or adjacent lab. current_strength_new 2ma, 4ma, 8ma, 10ma, 12 ma, 16 ma, 18 ma, 20 ma, 24 ma minimum_current or maximum_current drive strength for an output or bidi pin. stratixii_termination differential ?series 25 ohms with calibration? ?series 25 ohms without calibration? ?series 50 ohms with calibration? ?series 50 ohms without calibration? on-chip termination (or impedance matching) for an i/o pin.
6?20 altera corporation september 2008 hardcopy series handbook, volume 1 i/o assignment example script the following tcl script example specifies several different i/o constraints. ## signal-ball assignments set_location_assignment pin_ah5 -to addr_out[0] set_location_assignment pin_ah6 -to addr_out[1] set_location_assignment pin_aj5 -to data_in[0] set_location_assignment pin_aj6 -to data_in[1] set_location_assignment pin_aj32 -to resetn set_location_assignment pin_am17 -to ref_clk # i/o type and parameter assignments set_instance_assignment -name io_standard "1.5-v hstl class ii" -to addr_out[0] set_instance_assignment -name io_standard "1.5-v hstl class ii" -to addr_out[1] set_instance_assignment -name io_standard "1.5-v hstl class ii" -to data_in[0] set_instance_assignment -name io_standard "1.5-v hstl class ii" -to data_in[1] set_instance_assignment -name io_standard lvds -to resetn set_instance_assignment -name io_standard lvcmos -to ref_clk set_instance_assignment -name fast_input_register on -to data_in[0] set_instance_assignment -name fast_input_register on -to data_in[1] set_instance_assignment -name fast_output_register on -to addr_out[0] set_instance_assignment -name fast_output_register on -to addr_out[1] set_instance_assignment -name output_pin_load 10 -to addr_out[0] set_instance_assignment -name output_pin_load 10 -to addr_out[1] set_instance_assignment -name current_strength_new 16ma -to addr_out[0] set_instance_assignment -name stratixii_termination ?series 25 ohms without calibration?\ -to data_in[1] assigning timing constraints planning design timing constraints timing constraints ensure that a design compiled in the quartus ii software meets specific timing requ irements. when you target an fpga, you may decide not to apply a comple te set of timing constraints, choosing instead to fix any timing prob lems in your prototype system if and when they arise. hardcopy devices, however, cannot be modified using reconfiguration to fix timing problems, so it is critically important that a design is fully constrained. designs not fully constrained would result in significantly different timing characteristics between the prototype stratix ii fpga and the hardcopy ii device. by fully constraining a design, altera can guar antee that both the stratix ii fpga and the hardcopy ii device fully complies with your timing specifications.
altera corporation 6?21 september 2008 assigning timing constraints the minimum set of timing constraints for a hardcopy ii design are: clock settings (f max ) for each and every clock domain minimum and maximum delays for all i/o paths, including asynchronous reset and control i/o signals in addition, it is good design prac tice to develop timing constraints to cover: specific cross-clock domain timing requirements false paths multicycle paths in timequest, timing co nstraints are written in timequest sdc format and are read from an sdc file. an example file is demo_design . sdc . see ?using timequest? on page 6?30 . in the classic timing analyzer, ti ming constraints are applied using dedicated tcl commands and by assigning timing-specific attributes using the set_instance_assignment command. this section provides an overview of timing constraint development using tcl commands. f for more information on timing constraints, refer to the timing analysis section in volume 3 of the quartus ii handbook . specifying system clocks the most basic constraints that should be applied describe the clock for each clock domain. parameters usually specified for each clock are: clock period latency ( late_clock_latency / early_clock_latency assignments) uncertainty ( set_clock_uncertainty command) clock uncertainty specified with the set_clock_uncertainty command models any uncertainty in the clock period, including jitter, and is often used to in troduce some margin into the target clock frequency. the following example constraints illustrate clock definition for a design with two clock domains, clk_a and clk_b . in this case, both clocks run at 100 mhz, but with different clock latency and skew. ## example timequest sdc constraints defining clocks clk_a and clk_b create_clock -period 10.0 -name clk_a [get_ports clk_a] set_clock_latency -source -late 3.0 clk_a set_clock_latency -source -early 2.0 clk_a
6?22 altera corporation september 2008 hardcopy series handbook, volume 1 set_clock_uncertainty -to clk_a 0.25 create_clock -period 10.0 -name clk_b [get_ports clk_b] set_clock_latency -source -late 4.0 clk_b set_clock_latency -source -early 3.0 clk_b set_clock_uncertainty -to clk_b 0.25 input/output timing system clock parameters define the se tup and hold timing for register to register paths within each clock doma in. i/o timing parameters are used to describe i/o to register, and register to i/o timing. the set_input_delay constraint is used to specify the delay from a source external to the chip to an input pin, relative to a defined clock. the syntax for this command is given below. set_input_delay \ -clock < clock name> \ [-clock_fall] \ [-rise | -fall] \ [-max | -min] \ [-add_delay] \ [-reference_pin < pin or port> ] \ < delay value > \ < port pin list > the < clock name > argument specifies the reference clock for the delay. the < port pin list > argument is the top-level input signal for the design, and < delay value > is the external delay. the external delay is measured from the positive (rising) edge of < clock > unless the - clock_fall argument is specified. the -min and -max arguments are used to specify whether < delay value > is the minimum or maximum external delay, respectively. the set_output_delay constraint is similar to the set_input_delay constraint except that it specifies the delay from an output pin to its external destination relative to a clock. set_output_delay \ -clock < clock name> \ [-clock_fall] \ [-rise | -fall] \ [-max | -min] \ [-add_delay] \ [-reference_pin < pin or port> ] \ < delay value > \ < port pin list >
altera corporation 6?23 september 2008 assigning timing constraints as an example, the following tcl script specifies input and output min and max delays for two i/o signals. input data_in [ 0 ] has minimum and maximum external delays of 3 n s and 7 ns, respectively. output data_out [ 0 ] has minimum and maximum external delays of 4 ns and 8 ns, respectively. the external input delays for data_in [ 0 ] are relative to the positive edge of clock ref_clk and the external output delays for data_out [ 0 ] are relative to the negative edge of clock ref_clk . # tcl script setting i/o timing using set_input_delay and set_output_delay set_input_delay -clock ref_clk -max 7.0 [get_ports data_in[0]] set_input_delay -clock ref_clk -min 3.0 [get_ports data_in[0]] set_output_delay -clock ref_clk -max 8.0 [get_ports data_out[0]] set_output_delay -clock ref_clk -min 4.0 [get_ports data_out[0]] creating timing exceptions timing exceptions are used to correc t timing constraints not covered by clock settings and i/o timing setting s. the most common of these are multicycle paths and false paths. in timequest, multicycle paths are described using the set_multicycle_path constraint. the syntax for this constraint is: set_multicycle_path [-setup][-hold][-start] in classic timing analyzer, multicycle paths are described using the set_multicycle_assignment command. the sy ntax for this command is: tcl> set_multicycle_assignment [-comment < comment >] \ [-disable] [-end] [-from < from_list >] \ [-hold] [-remove] [-setup] [-start] \ [-to < to_list >] < path_multiplier > in either timing analyzer, multicyc le assignments are made with the -setup argument, to specify the maximum number of cycles, or with the -hold argument, to specify the minimum number of cycles for a path. false paths describe paths that sh ould not be included in timing optimization or analysis operations. in the quartus ii software, there are a number of ways to describe false paths. by default, in classic timing analyzer, feedback from the output to input side of bi directional i/o, read-while-write paths through memo ries, and cross-clock domain paths are not timed during optimi zation or timing analysis. by default, in time quest, cross-clock doma in paths are timed.
6?24 altera corporation september 2008 hardcopy series handbook, volume 1 f to change these default settings, refer to the timing settings section in the quartus ii support of ha rdcopy series devices chapter in volume 1 of the quartus ii handbook . in timequest, the constraint set_false_path is used to describe paths that should not be included in timing opti mization or analysis. the syntax for this constraint is: tcl> set_false_path \ [-from < from list >] \ [-to < to list >] \ [-thru < thru list >] in classic timing analyzer, the mo st common command for controlling false paths is the set_timing_cut_assignment command. the syntax for this command is: tcl> set_timing_cut_assignment \ [-comment ] \ [-disable] \ [-from ] \ [-remove] \ [-to < to_pin_list >] all paths between nodes in the < from_pin_list > to nodes in the < to_pin_list > are excluded from timing optimization and analysis operations. example of timequest sdc constraints # timing assignments # ================== create_clock ?period 10.0ns -name ref_clk ref_clk set_clock_latency -late 3 ref_clk set_clock_latency -early 2 ref_clk set_clock_uncertainty ?hold ?to ref_clk 0.250ns set_clock_uncertainty ?setup ?to ref_clk 0.250ns # input delay of 6ns (max) & 2ns (min) for bus data_in[1:0] set_input_delay ?clock ref_clk ?max 6 data_in set_input_delay ?clock ref_clk ?min 2 data_in # output delay of 6ns (max) & 2ns (min) for bus data_out[1:0] set_output_delay ?clock ref_clk ?max 6 data_out set_output_delay ?clock ref_clk ?min 2 data_out # don?t care about timing on the resetn net. set as false path set_false_path -from resetn
altera corporation 6?25 september 2008 compiling the stratix ii prototype design example of classic timing analyzer tcl script # timing assignments # ================== create_base_clock ?fmax 100 mhz ?target ref_clk ref_clk set_instance_assignment -name late_clock_latency 3ns -to ref_clk set_instance_assignment -name early_clock_latency 2ns -to ref_clk set_clock_uncertainty ?hold ?to ref_clk 0.250ns set_clock_uncertainty ?setup ?to ref_clk 0.250ns # input delay of 6ns (max) & 2ns (min) for bus data_in[1:0] set_input_delay ?clk_ref ref_clk ?max ?to data_in 6.0ns set_input_delay ?clk_ref ref_clk ?min ?to data_in 2.0ns # output delay of 6ns (max) & 2ns (min) for bus data_out[1:0] set_output_delay ?clk_ref ref_clk ?max ?to data_out 6.0ns set_output_delay ?clk_ref ref_clk ?min ?to data_out 2.0ns # don?t care about timing on the resetn net. set as false path set_timing_cut_assignment -from resetn this section has provided an overview of tcl commands for applying timing constraints. f for more information on the applicat ion of timing constraints using tcl commands, refer to the tcl packages and commands chapter in the quartus ii scripting reference manual . compiling the stratix ii prototype design once all global assignments, resource assignments, and timing assignments have been specified, the ne xt step in the design process is to compile the stratix ii fpga prototype design. the execute_flow command is provided for this purp ose and supports various arguments affecting the compilation process. the syntax for this command is: tcl> execute_flow \ [-analysis_and_elaboration] \ [-attempt_similar_placement] \ [-check_ios] \ [-check_netlist] \ [-compile] \ [-compile_and_simulate] \ [-early_timing_estimate] \ [-eco] [-export_database] \ [-fast_model] \ [-generate_functional_sim_netlist] \ [-import_database]
6?26 altera corporation september 2008 hardcopy series handbook, volume 1 the switches relevant to prototype stratix ii and hardcopy ii design are listed in table 6?8 . 1 it is important to note that the hardcopy switches for the execute_flow command are for hardcopy stratix designs, not hardcopy ii designs. the simplest way to run the execute_flow command is to use the -compile switch. tcl> execute_flow -compile running the execute_flow command in this way executes the four stages of the quartus ii compilation flow with default settings for each stage: analysis and synthesis fitter timing analysis assembler table 6?8. execute_flow tcl command switches switch description analysis_and_elaboration perform synthesis and mapping to the target altera technology attempt_similar_placement runs attempt similar placement check_ios verify i/o assignments check_netlist perform syntax checks on the netlist compile execute the quartus ii compilation flow compile_and_simulate as for compile, but also run simulation early_timing_estimate runs the early timing estimator eco executes a fitter eco compilation export_database exports a version-compatible database fast_model runs timing analysi s (fast mode analysis) generate_functional_sim_netlist generate a simulation netlist import_database imports a version-compatible database
altera corporation 6?27 september 2008 compiling the hardcopy ii design the design assistant and timing constraint checks are run if they are enabled in the quartu s ii settings file. you should check i/o assignments to avoid problems in downstream compile operations. to do this, the execute_flow compilation is broken into three steps: 1. tcl > execute_flow - analysis_and_elaboration 2. tcl > execute_flow - check_ios 3. tcl> execute_flow -compile it should be noted that, in the interests of clarity and brevity, the tcl fragments given here do not incorpor ate any error checking. however, it is good practice to include code in yo ur tcl scripts that checks for success as your design proceeds . in the case of the execute_flow procedure, the return value can be used with the tc l catch command to handle success or failure. the example below shows one option for doing this. # determine if compilation was successful and # print out a personalized message. if {[catch {execute_flow -compile} result]} { puts "\nresult: $result\n" puts "error: compilation failed. see report files.\n" } else { puts "\ninfo: compilation was successful.\n" } f for more information on the execute_flow command, refer to the command description in the tcl packages and commands chapter in the quartus ii scripting reference manual . compiling the hardcopy ii design once the stratix ii fpga prototype de sign is compiled and verified, you can compile the hardcopy ii revision of the design. this is a two-step process: 1. create the hardcopy ii companion revision. 2. compile the hardcopy ii companion revision. to create the hardcopy ii version of the design, run the execute_hardcopyii tcl command with the - create_companion option: tcl> execute_hardcopyii -create_companion demo_design_hcii
6?28 altera corporation september 2008 hardcopy series handbook, volume 1 this command initializes the database for the hardcopy ii revision and creates a new qsf file (in this example, demo_design_hcii.qsf ), ensuring that all constraints for the stratix i i fpga revision are ported over. next, the current working revision fo r the quartus ii project is changed to the hardcopy ii revision and the design is compiled for the hardcopy ii device target: tcl> set_current_revision demo_design_hcii tcl> execute_flow -compile as with the prototype stratix ii revision, report files are generated in the project directory for each of the tools that are executed. understanding report files the execute_flow command generates a number of report files in the project directory. these files summ arize messages displayed on the console during compilation and prov ide additional information about the design. the name of each re port file follows the format < revision >< tool short name > .summary and < revision > .rpt , where < revision > is the revision name of the current design. the .summary file contains a brief summary of messages and results from the tool while the .rpt file contains more detailed messages and information. for a hardcopy ii project, two sets of report files are generated: one for the stratix ii prototype fpga revision and one for the hardcopy ii revision. table 6?9 describes the different report files. 1 the tcl report package provides a powerful collection of procedures for customizing and managing report files related to the quartus ii fitter and ti ming analysis engines. f for more information on customizing an d managing report files, refer to the tcl packages and command s report section of the quartus ii tcl reference manual . table 6?9. stratix ii compile report file descriptions (part 1 of 2) switch tool description < revision > .map.rpt analysis & synthesis synthesis settings, source files, messages, and resource usage. < revision > .map.eqn analysis & synthesis implem entation equations and device resource instantiations. < revision > .fit.rpt fitter fitter settings, layout opti mizations, resources, pin-out, and messages. < revision > .fit.eqn fitter implemented equations and device resource instantiations after fitting. < revision > .drc.rpt design assistant design rule se ttings, violations, and messages.
altera corporation 6?29 september 2008 comparing fpga and hardcopy revisions comparing fpga and hardcopy revisions before submitting the hardcopy ii project to the altera design center, it should be checked against the strati x ii prototype fpga revision. to do this, run the execute_hardcopyii tcl command with the -compare option from the quartus_sh shell: tcl> execute_hardcopyii -compare running this command generates a report file and summary file in the project directory. these files are called < revision_name > .rec.rpt and < revision_name >. rec.summary . the command checks to verify that the following items conform to hardcopy ii design rules and are consistent between the hardcopy ii and stratix ii revisions: source design files and device netlist files user clock assignments timing constraints (assignments) i/o location and type assignments pll parameters memory implantation parameters dsp implementation parameters global resource properties properties of all other device resources used any errors or failures in comparison are reported in the .rec report files. an example .rec file is given below. note that for this example, the design comparison checks in the hardcopy ii companion revision comparison summary table are all marked passed, indicating that the hardcopy ii design in the quartus ii software is fi nished and ready for hand-off to the back-end engineering team in the altera design center. you must resolve any failures that show up in the comparison summary before you proceed any further with your design. < revision > .upc.rpt timing constraint checker constraint coverage information. < revision > .asm.rpt assembler assembler settings, .pof and .sof output file options, and messages. < revision > .rec.rpt companion revision comparison a status report on the structural comparison between the hardcopy ii revision and the stratix ii prototype design. < revision > .flow.rpt flow resource summary and execution time for each tool in the flow. this report is updated as different tools in the flow complete. < revision > .sta.rpt timequest timequest ti ming analysis report. table 6?9. stratix ii compile report file descriptions (part 2 of 2) switch tool description
6?30 altera corporation september 2008 hardcopy series handbook, volume 1 hardcopy ii companion revision comparison report for demo_design_hardcopyii wed sep 20 15:30:07 2006 version 6.0 build 202 06/20/2006 service pack 1 sj full version --------------------- ; table of contents ; --------------------- 1. legal notice 2. hardcopy ii companion revision comparison summary 3. atom netlist comparison summary 4. dsp information 5. hardcopy ii companion revision comparison messages +--------------------------------------------------------------------------------------+ ; hardcopy ii companion revision comparison summary ; +--------------------------------------------------+-----------------------------------+ ; hardcopy ii companion revision comparison status ; analyzed - wed sep 20 15:29:55 2006 ; ; quartus ii version ; 6.0 build 202 06/20/2006 sp 1 sj full version ; ; revision name demo_dsign_hardcopyii ; ; top-level entity name ; demo_design ; ; family ; stratix ii ; ; compare status ; passed (14/14) ; ; source files compared ; passed (121/121) ; ; assignments compared ; passed ; ; user clocks compared ; passed (0/0) ; ; resource counts compared ; passed (5/5) ; ; i/o structure compared ; passed (130/130) ; ; package pins compared ; passed (1020/1020) ; ; pll structure compared ; passed (1/1) ; ; pll clocks compared ; passed (2/2) ; ; timing constraints compared ; passed (3/3) ; ; ram information compared ; passed (10/10) ; ; dsp information compared ; passed (100/100) ; ; global resources compared ; passed (8/8) ; ; atom compared ; passed (335084/335084) ; ; atom netlist compared ; passed (1/1) ; +--------------------------------------------------+-----------------------------------+ performing static timing analysis static timing analysis in the quartus ii software the global assignments made for the stratix ii prototype and hardcopy ii revisions ensure that static timing analysis (sta) is run for both fast and slow operating conditio ns and both setup and hold timing is verified. using timequest you can run the timing analysis inde pendent of the compile process in one of two ways: 1. use the execute_module -tool sta tcl command to run a timing analysis tcl script in quartus_sta from within the basic quartus shell, quartus_sh .
altera corporation 6?31 september 2008 performing static timing analysis 2. run the quartus_sta interactive tcl shell independently and execute tcl commands and scripts at the tcl prompt. using classic timing analyzer you can run the timing analysis inde pendent of the compile process in one of two ways: 1. use the execute_module -tool tan tcl command to run a timing analysis tcl script in quartus_tan from within the basic quartus shell, quartus_sh. 2. run the quartus_tan interactive tcl shell independently and execute tcl commands and scripts at the tcl prompt. f for more information on running static timing analysis in the quartus ii software, refer to the timing analysis section in the quartus ii handbook . f for tcl commands related to static timing analysis , refer to the timing section of the tcl packages and commands in the quartus ii scripting reference manua l. static timing analysis in primetime the quartus ii software can also generate files required to run sta in synopsys? primetime. the following example tcl commands direct the quartus ii software to generate primetime files for sta. ## tcl script to generate primetime sta file output execute_module -tool sta -args --tq2pt execute_module -tool eda -args "--tool primetime --format verilog --timing_analysis" the files generated by the quartu s ii software are organized in a subdirectory within the project director y. for example, after compiling a stratix ii prototype design ( demo_design ), the following verilog ( .vo ) sdf ( .sdo ) and primetime tcl script ( .tcl ) are created in the project directory. timing\ primetime\ demo_design_v.sdo demo_design.pt.tcl demo_design.collections.sdc demo_design.constraints.sdc the tcl script includes all timing constraints applied during the quartus ii software compilation.
6?32 altera corporation september 2008 hardcopy series handbook, volume 1 hardcopy ii example tcl script the following script draws together the tcl ideas discussed thus far into a top-level tcl script for the quartus_sh tcl shell. this script implements a hardcopy ii design called demo_design. it begins by creating a new project, called demo_design , compiling the stratix ii fpga prototype, creating a hardcopy ii companion revision and then compiling the companion revision. finally, the revisi on comparison tool is run to verify that both revisions are consistent. in this example, global, pin, and ti ming assignment scripts are read into the top-level script using the tcl source command. the sourced scripts are listed after the top-level script listing. top-level example script demo_design.tcl ## demo_design.tcl ## top-level script for executing a hardcopy ii design in quartus_sh -s load_package flow ## open of create the stratix ii fpga prototype revision if [is_project_open] project_close if {[project_exists demo_design]} { project_open demo_design } else { project_new demo_design } ## apply global design settings source global_assignments.tcl ## apply i/o assignments source pin_assignments.tcl ## apply fpga timing constraints source timing_assignments.tcl ## compile the stratix ii fpga prototype design execute_flow -compile # #create and switch to the hardcopy ii target revision execute_hardcopyii -create_companion demo_design_hcii project_close project_open demo_design -revision demo_design_hcii ## compile the hardcopy ii design revision execute_flow -compile ## check the hardcopy ii revision and make sure it matches the fpga ## design execute_hardcopyii -compare
altera corporation 6?33 september 2008 hardcopy ii example tcl script ## generate a hardcopy ii handoff report execute_hardcopyii -handoff_report ## archive the hardcopy ii handoff files into ## the file named "demo_design_hcii_handoff.qar" execute_hardcopyii -archive demo_design_hcii_handoff.qar ## quit quartus_sh -s qexit ## end of demo_design.tcl global assignments script global_assignments.tcl the global_assignments.tcl script source in the top-level script, demo_design.tcl prepares global variables, target devices, and revision names for the hardcopy ii project: ## global_assignments.tcl ## source design file settings ## =========================== set_global_assignment -name verilog_file demo_design.v set_global_assignment -name verilog_file example_ram.v ## constraint file settings for timequest ## ============================ set_global_assignment -name use_timequest_timing_analyzer on set_global_assignment -name sdc_file demo_design.sdc ## stratix ii prototype fpga target settings ## ========================================= set_global_assignment -name family "stratix ii" set_global_assignment -name device ep2s90f1020c4 set_global_assignment -name top_level_entity demo_design ## hardcopy ii companion revision and target settings ## ================================================== set_global_assignment -name companion_revision_name \ demo_design_hardcopyii set_global_assignment -name device_technology_migration_list HC230f1020 ## design assistant assignments and settings required for hardcopy ii ## ================================================================== set_global_assignment -name enable_drc_settings on set_global_assignment -name error_check_frequency_divisor 1 set_global_assignment -name report_io_paths_separately on ## the following assignments are classic timing analyzer only and ## are not used by timequest. ## ================================================== set_global_assignment -name flow_enable_timing_constraint_check on set_global_assignment -name do_combined_analysis on set_global_assignment -name ignore_clock_settings off
6?34 altera corporation september 2008 hardcopy series handbook, volume 1 set_global_assignment -name enable_recovery_removal_analysis on set_global_assignment -name enable_clock_latency on ## end of global_assignments.tcl pin assignments script pin_assignments.tcl the pin_assignments.tcl script run from the top-level script, demo_design . tcl, specifies top-level design signal to package ball assignments and i/o parameters: ## pin_assignments.tcl set_location_assignment pin_ah5 -to addr_out[0] set_location_assignment pin_ah6 -to addr_out[1] set_location_assignment pin_aj5 -to data_in[0] set_location_assignment pin_aj6 -to data_in[1] set_location_assignment pin_aj32 -to resetn set_location_assignment pin_am17 -to ref_clk ## i/o type and parameter assignments set_instance_assignment -name io_standard "1.5-v hstl class ii" -to addr_out[0] set_instance_assignment -name io_standard "1.5-v hstl class ii" -to addr_out[1] set_instance_assignment -name io_standard "1.5-v hstl class ii" -to data_in[0] set_instance_assignment -name io_standard "1.5-v hstl class ii" -to data_in[1] set_instance_assignment -name io_standard lvds -to resetn set_instance_assignment -name io_standard lvcmos -to ref_clk set_instance_assignment -name fast_input_register on -to data_in[0] set_instance_assignment -name fast_input_register on -to data_in[1] set_instance_assignment -name fast_output_register on -to addr_out[0] set_instance_assignment -name fast_output_register on -to addr_out[1] set_instance_assignment -name output_pin_load 10 -to addr_out[0] set_instance_assignment -name output_pin_load 10 -to addr_out[1] ## end of pin_assignments.tcl timequest constraint file demo_design.sdc timequest reads the sdc file demo_design . sdc and applies timing constraints for the system clock, ref_clk , and i/o-to-core timing specifications. ## constraints.sdc create_clock ?period 10.0 mhz -name ref_clk [get_ports ref_clk] set_clock_latency -late 3 ref_clk set_clock_latency -early 2 ref_clk set_clock_uncertainty ?hold ?to ref_clk 0.250 set_clock_uncertainty ?setup ?to ref_clk 0.250 # input delay of 6ns (max) & 2ns (min) for bus data_in[1:0] set_input_delay ?clock ref_clk ?max 6 [get_ports data_in]
altera corporation 6?35 september 2008 summary set_input_delay ?clock ref_clk ?min 2 [get_ports data_in] # output delay of 6ns (max) & 2ns (min) for bus data_out[1:0] set_output_delay ?clock ref_clk ?max 6 [get_ports data_out] set_output_delay ?clock ref_clk ?min 2 [get_ports data_out] # don?t care about timing on the resetn net. set as false path set_false_path -from [get_ports resetn] ## end of timing_assignments.tcl timing assignments script timing_assignments.tcl if you are using classic timing analyzer, the timing_assignments.tcl script is run from the top-level script, demo_design . tcl . this script applies timing constraints for the system clock, ref_clk , and i/o-to-core timing specifications. ## timing_assignments.tcl create_base_clock ?fmax 10.0ns ?target ref_clk ref_clk set_instance_assignment -name late_clock_latency 3ns -to ref_clk set_instance_assignment -name early_clock_latency 2ns -to ref_clk set_clock_uncertainty ?hold ?to ref_clk 0.250ns set_clock_uncertainty ?setup ?to ref_clk 0.250ns # input delay of 6ns (max) & 2ns (min) for bus data_in[1:0] set_input_delay ?clk_ref ref_clk ?max ?to data_in 6.0ns set_input_delay ?clk_ref ref_clk ?min ?to data_in 2.0ns # output delay of 6ns (max) & 2ns (min) for bus data_out[1:0] set_output_delay ?clk_ref ref_clk ?max ?to data_out 6.0ns set_output_delay ?clk_ref ref_clk ?min ?to data_out 2.0ns # don?t care about timing on the resetn net. set as false path set_timing_cut_assignment -from resetn ## end of timing_assignments.tcl summary this chapter introduced script-based design for hardcopy ii devices using the quartus ii interactive tcl shell. this approach provides you with an alternative to gui-based desi gn for certain situations such as remote-terminal quartus ii execution, design flow automation, or even if you are simply more comfortable operating in a scripting environment.
6?36 altera corporation september 2008 hardcopy series handbook, volume 1 document revision history table 6?10 shows the revision history for this chapter. table 6?10. document revision history date and document version changes made summary of changes september 2008, v1.3 updated chapter number and metadata. ? june 2007, v1.2 minor text edits. ? december 2006 v1.1 updates for the quartus ii software version 6.1.0 added information on the tcl command-line executable quartus_sta, newly available in quartus ii software version 6.1.0, and recommended for use in hardcopy ii design timing analysis. updated figure 6?1. updated table 6?1, table 6?2, and table 6?3. added revision history. a medium update to the chapter, due to changes in the quartus ii software version 6.1 release. march 2006 formerly chapter 15; no content change. ? october 2005 v1.0 initial release of script-based design for hardcopy ii devices. ?
altera corporation 7?1 september 2008 7. timing constraints for hardcopy ii devices introduction in a stratix ? ii fpga design, a complete and accurate set of timing constraints is often not critical to ac hieving a fully functioning product. the reconfigurability of the fpga mean s that if a timing-related problem occurs during hardware test and verification, the device can be reprogrammed to correct it. no asic re-spin or board-level work-around is necessary and the fix can be implemented in a timely and cost-effective way. in contrast, a hardcopy ? ii design results in a mask-programmed, structured asic device. timing problems may result in long design-change turn-around times and high nre costs. to ensure a smooth transition through the quartus ? ii software and back-end design in the altera ? hardcopy design center (hcdc), altera strongly recommends that you use the timeques t timing analyzer provided with the quartus ii software and that you follow the timing considerations and timing constraint re commendations given in this chapter. use of the timequest timing analyzer for design review 2 (dr2) in the hardcopy ii design flow will soon be mandatory. the timequest timing analyzer is a co mplete static timing analysis tool that you can use as a sign-off tool fo r altera fpgas and structured asics. as fpga devices become denser and faster, they are the targets of complex designs and applications that previously were implemented in asics. these complex designs push the limits of the traditional classic timing analyzer, affecting design er productivity. the quartus ii timequest timing analyzer, in contrast, works well on complex designs. its intuitive user interface, supp ort of industry-standard synopsys design constraints (sdc) format, and scripting capabilities all result in increased productivity and efficiency. f for more information on the features and capabilities of the timequest timing analyzer, refer to the timequest timing analyzer chapter in volume 3 of the quartus ii handbook . this chapter includes th e following information: a description of timing-related differences between hardcopy ii structured asics and stratix ii fpgas descriptions and a comparison of the timequest timing analyzer and the classic timing analyzer h51028-2.2
7?2 altera corporation september 2008 hardcopy series handbook, volume 1 an explanation of the use of timi ng constraints in the quartus ii software, including some of the important timing-related checks reported by the hardcopy ii advisor and design assistant timing constraint recommendation s for your hardcopy ii project and recommendations for handling le gacy designs that use timing constraints not supported in the hardcopy ii design flow hardcopy ii versus stratix ii timing the back-end design of your hardco py ii structured asic includes timing closure in ac cordance with the timing sp ecification achieved in the quartus ii software for the stratix ii fpga prototype and hardcopy ii device. however, you should be aware th at this does not mean that actual path timing in the stratix ii fpga is duplicated in the hardcopy ii device. in fact, because of the archit ectural differences between stratix ii and hardcopy ii devices, you should expect that while internal and i/o path timing are within whatever timing constrai nts you applied, actual path delays are different. the key factors that impact timing differences between stratix ii and hardcopy ii devices are listed below. the hardcopy ii die is significantly smaller than its stratix ii counterpart coarse-grain adaptive logic modules (alms) in stratix ii devices are mapped to fine-grain hcell macros in hardcopy ii devices design connections are implemented using custom metal routing in hardcopy ii devices hardcopy ii devices contain no sram-configurable programmable connection points leaf sub-trees in hardcopy ii gl obal clock networks are custom routed the following sections briefly descri be the effect of these factors on hardcopy ii timing characteristics. internal register-to-register timing internal timing is the timing of paths from register to register within core logic. internal timing is dependent on the transport delays of logic elements on register-to-register path s and the overall effects of parasitic capacitance, parasitic resistance, and crosstalk on routing connections between those logic elements. user-logic implementation in hardcopy ii devices is more area efficient and often has improved timing when compared with the stratix ii fpga. these advantages are the result of re-mapping the coarse-grain,
altera corporation 7?3 september 2008 introduction programmable alms in stratix ii de vices to fine-grain hcell macros in hardcopy ii devices. all alm functions are re-mapped to hcells in hardcopy ii devices. usin g fine-grain hcells eliminates the need for the programmable routing multiplexers (muxs) found inside the stratix ii alm blocks. this reduces the number of levels of logic required to implement alm functions from the stratix ii device. consequently, the transport, or propagation, delays as sociated in the stratix ii fpga with alms in register-to-register paths ar e smaller in the hardcopy ii device. the hardcopy ii device does not require configuration sram, so die size is significantly smaller than for stratix ii counterpart devices. one effect of reduced die size is that overall routing length is shorter. in addition, hardcopy ii devices use customizat ion of metal layers 5 and 6 to implement user-logic connections. the fact that no configuration sram is required eliminates the need fo r sram-configurable routing switches and programmable connection points , all of which adversely affect timing. therefore, overall, parasi tic capacitance and resistance and crosstalk levels are often lower in the hardcopy ii device, leading to faster connections than those found in the stratix ii fpga. faster logic element implementation and faster routing in hardcopy ii devices generally result in faster register-to-register paths and higher overall clock frequencies. softwa re place-and-route tools have a significant impact on timing results, however, so there are cases where stratix ii register-to-register paths ar e faster than the corresponding paths in the hardcopy ii device. the internal timing performance of digital signal processing (dsp) functions is similar in a stratix ii fpga and its corresponding hardcopy ii device. in stratix ii fpgas, dsp functions are usually implemented in the embedded dsp blocks. these dsp blocks provide optimal area and performance for dsp functions. in hardcopy ii devices, the same dsp functions are implemen ted in hcell dsp macros, which are designed to match the functionality and timing of the dsp blocks in stratix ii devices. however, the timi ng performance of paths between the dsp functions and other core logic is generally faster in the hardcopy ii device than in the stratix ii fpga. ram-block access time is similar in a stratix ii fpga and its corresponding hardcopy ii device. however, as for dsp functions, the timing performance of paths between the ram blocks and other core logic is generally faster in the hardcopy ii device than in the stratix ii fpga.
7?4 altera corporation september 2008 hardcopy series handbook, volume 1 i/o path timing the actual timing and parametric characteristics of i/o cells in hardcopy ii devices are very similar to those in stratix ii devices. you should expect, however, to see differe nces in i/o signal path timing. these differences are primarily be cause of timing differences in core-to-i/o and cl ock distribution. for core-to-i/o timing, one of the larg est influencing fac tors is the timing behavior of signal path s, as described in the ?internal register-to-register timing? section. in general, core-to-i/o and i/o-to-core timing are different between hardcopy ii and stratix ii devices. the other major influence on i/o ti ming is the cloc k distribution differences between hardcopy ii and st ratix ii devices. shorter, faster clock trees, custom clock tree buffe ring and custom routing of leaf sub-trees in hardcopy ii mean that insertion delays, latencies, skew characteristics, jitter, and pll compen sation are different from the stratix ii fpga. the effect of th is is described in the ?clock distribution effects? section. clock distribution effects the hardcopy ii structured asic has a clock distribution scheme that is similar to that in stratix ii fpga s with some notable differences: there are no sram-programmable switches and routing connections reduced die-size means shorter ov erall clock tree routing length leaf sub-trees of clock networks are custom routed using customized metal mask layers these physical differences affect clock distribution characteristics across the device. timing characteristics most affected are: clock tree latency and clock insertion delay clock skew clock jitter pll compensation delays in general, clock tree latencies are smaller in the hardcopy ii device because of shorter routing length and the absence of sram-programmable switches. as a re sult, you should expect that any clock insertion delays that are modeled will also be shorter.
altera corporation 7?5 september 2008 hardcopy ii timing closure methodology the most significant impact of reduced clock tree latency is the changes in core-to-i/o and i/o-to-core timing. for example, if an i/o register is clocked earlier because of reduced clock latency, the arrival time of the register output at the device pin is reduced. similarly, if an input register is clocked earlier, the setup time for that register is also earlier, and the hold time requirement is relaxed. the quartus ii software accommodate s these differences to ensure that your timing requirements are satisf ied. however, you should be aware that reduced clock insertion delay causes i/o timing differences between your stratix ii fpga prototype an d a hardcopy ii-structured asic. pll characteristics many of the effects described in the ?clock distribution effects? section also apply to the clock outputs fr om plls between stratix ii and hardcopy ii devices. the quartus ii software implements compensation delays for plls in your hardcopy ii device to account for differences in pll clock distribution. this ensures that the compensation modes used in the stratix ii fpga are also used in the hardcopy ii structured asic. hardcopy ii timing closure methodology to achieve timing closure for your ha rdcopy ii structured asic, it is imperative that you use a complete set of accurate timing constraints throughout the flow. for the strati x ii fpga prototype, although you may verify timing and functionality in hardware, it is essential that the design be compiled and verified in the quartus ii software using a complete set of timing constraints. these constraints feed forward to the hardcopy ii revision of the projec t, and ultimately to the hardcopy design center (hcdc). the back-end design of your structured asic in the hcdc ensures that it conforms to whatever timing constraints are satisfied in the quartus ii software. it is importan t to remember that while the quartus ii timing constraints are respected, the actual stratix ii fpga prototype timing you observe in hardware is not duplicat ed in the hardcopy ii structured asic. the timing differences betw een the stratix ii device and the hardcopy ii structured asic are inco nsequential as long as both are checked against a complete set of timing constraints. hardcopy ii timing closure flow hardcopy ii timing clos ure methodology is comprehensive and includes both the timequest timing analyzer and classic timing analyzer in the quartus ii software, an interface to a third-party static timing analyzer, and fpga-prototype timing verification in the hardware.
7?6 altera corporation september 2008 hardcopy series handbook, volume 1 altera recommends you use the ti mequest timing analyzer. you can specify that the timequest timing an alyzer be used by the quartus ii software rather than the defa ult classic timi ng analyzer. the timequest timing analyzer valida tes the timing performance of all logic in your design using an indust ry-standard constraint, analysis, and reporting methodology. it provides po werful timing analysis features that enable thorough timing analysis of high-performance designs. the benefits of using timequest for timi ng analysis include these features: native sdc support ?you can leverage this powerful industry-standard timing constraint format to achieve a higher degree of productivity by usin g and reusing sdc- and tcl-based scripts. fast on-demand and interactive data reporting ?this feature saves time by allowing you to request mo re detailed timi ng analysis on critical paths only. a powerful gui reports the timing analysis data in an intuitive graphical form at that complements the fast, on-demand data reporting, fu rther enhancing productivity. classic timing analyzer support s hardcopy ii ti ming analysis. however, timequest provides more po werful timing analysis features. some classic timing analyzer timing constraints may not be translated from the quartus setting file to sdc format constraints when the design is transferred to the hcdc, becaus e translating these constraints is difficult and error-prone and often re quires detailed analysis of the particular context in which the constraint is used. the timing closure meth odology used in the quartus ii software for a hardcopy ii design is shown in figure 7?1 . this diagram shows the fpga-first static timing analysis flow for either the timequest timing analyzer or the classic timing anal yzer. for the hardcopy ii first flow, the methodology is the same except that the hardcopy ii compilation is performed before the st ratix ii compilation.
altera corporation 7?7 september 2008 hardcopy ii timing closure methodology figure 7?1. stratix ii firs t timing closure flow note (1) note to figure 7?1 : (1) timing constraints are required in stratix ii revision and ha rdcopy ii revision. the timequest timing analyzer supports industry-standard sdc files ( .sdc ) and classic timing analyzer supports quartus setting file ( .qsf ). as you can see from figure 7?1 , timing constraints are used very early in the quartus ii design flow. during the strati x ii fpga prototype compilation, these constraints are used as the timing target for timing-driven compilation. when th e compilation is complete, the timequest timing analyzer or classic timing analyzer reports timing results for your design. any failed timing reports mean that you must either modify your timing constraint s, change your compile settings and recompile, or both. in addition, the ti ming constraint checkers in both timequest and classic timi ng analyzer report the unconstrained timing paths. see ?using the timequest timi ng analyzer? on page 7?8 for details. for timing verification in third-party tools, the quartus ii stratix ii revision timing constraints compilation constraint coverage checks static timing analysis fpga prototyping hardcopy ii revision timing constraints industry standard sdc timing constraints stratix ii design setup compilation constraint coverage checks static timing analysis hardcopy design center handoff revision comparison hardcopy ii design setup hardcopy ii structured asic design fpga prototype design
7?8 altera corporation september 2008 hardcopy series handbook, volume 1 software can generate static timing analysis scripts fo r use in synopsys primetime tools. in addition, timi ng can be further verified in third-party, timing-d riven simulation tools. when software timing verification of the stratix ii prototype fpga is complete, you can verify your prototype in hardware. it is a requirement of the hardcopy ii design flow that you fully verify th e stratix ii fpga prototype timing over the range of op erating conditions that your design is exposed to. the next step is to create and compile your hardcopy ii design revision. by default, your hardcopy ii compil ation is run with the same timing constraints used during the compilatio n and verification of your stratix ii fpga. if you wish to change the ta rget timing specifications for the hardcopy ii revision, you can do so by changing the hardcopy ii timing constraints before compiling. when the hardcopy ii compilation is complete, just as you do after the stratix ii compilation, run timequest or classic timing analyzer to check timing results. you should review and resolve any timing failures that are reported. one of the final steps in the hardcopy ii design flow in the quartus ii software is the revision comparison check. part of this check compares timing constraints and settings betw een the stratix ii and hardcopy ii revisions of the project. any differenc es between the two are reported. if you change the timing constraints after completing stratix ii fpga prototyping, the revision compare tool will report the change and you will be asked to waive this difference in the design review. when your quartus ii design is tran sferred to the hcdc, it includes an industry-standard (sdc) version of th e hardcopy ii timing constraints. this version is the set of legal timi ng constraints for the design that include commands only from the sdc package in the quartus ii software. for the hardcopy ii design flow, you may not use any commands except those in the sdc package in the quartus ii soft ware. in addition, you must correct all timing constr aints that generate wa rning messages in the quartus ii software. f for more detailed information on the quartus ii sdc package, refer to the sdc package section in the tcl packages and commands chapter of the quartus ii scripting reference manual. using the timequest timing analyzer the timequest timing analyzer plays an integral part in the quartus ii hardcopy ii timing closure flow, from the specification of timing constraints to the verification of design requirements.
altera corporation 7?9 september 2008 hardcopy ii timing closure methodology the timequest timing analyzer prov ides a number of timing checks during the hardcopy ii design flow . the hardcopy ii advisor guides you to launch the timequest timing an alyzer for these timing checks and ensures that the design is fully constrained, as shown in figure 7?2 . figure 7?2. timequest timing-related se ttings in the hardcopy ii advisor all timing paths must be full y constrained. the timequest report_ucp command (or the timequest gui tasks pane option report unconstrained paths ) generates a series of reports that detail all unconstrained paths in your design. these reports list unconstrained setup, hold, recovery, and removal ti ming paths in the design. you must correct any design errors the report shows you by applying additional constraints before running static timing analysis. the timequest timing analyzer supports most constraints in the sdc format for the hardcopy series of devices. the timequest timing analyzer constraints are specified in commands from two tcl packages in the quartus ii software. these packages are the sdc package and the sdc_ext package. the hardcopy ii design flow requires that all timing constraints be specified in commands from the sdc version 1.5
7?10 altera corporation september 2008 hardcopy series handbook, volume 1 specification, as provided in the sdc package. quartus ii software returns warning messages in the early stage of the compilation for hardcopy ii design flow if the sdc file contains any constraints that use commands from the timequest extension to the sdc version 1.5 specification, which are provided in the sdc_ext package. to enable a smooth transfer of the sdc file to the hcdc (hardcopy desi gn center) for back-end design, you should avoid using comma nds and options from the sdc_ext package. f for more detailed information on the quartus ii sdc and sdc_ext packages, refer to the sdc package section in the tcl packages and commands chapter of the quartus ii scripting reference manual and to the sdc and timequest api reference manual. in addition to these timing-related checks, you should review the quartus ii timing repo rt sections in the compilation report and resolve any timing violations that may be reported ( figure 7?3 ). figure 7?3. timequest unconstrained timing path report
altera corporation 7?11 september 2008 hardcopy ii timing closure methodology f for more detailed information about th e features and capabilities of the timequest timing anal yzer, refer to the timequest timing analyzer chapter in volume 3 of the quartus ii handbook . using classic timing analyzer classic timing analyzer analyzes the delay of every design path and analyzes all timing requir ements to ensure correc t circuit operation. as part of the compilation flow, the quartus ii software automatically performs static timing analysis so that you do not need to launch a separate timing analysis tool. classi c timing analyzer checks every path in the design against your timing co nstraints for timing violations and reports results in the timing analys is reports, giving you immediate access to the data. quartus ii timing related checks and settings the classic timing analyzer provides a number of timing related checks as you go through a hardcopy ii de sign flow. the hardcopy ii advisor can guide you through these checks an d ensure that you perform all steps required to successfully complete a hardcopy ii design. f for more information on the hard copy ii advisor and the checks performed by the design assistant, refer to the design guidelines for hardcopy series devices chapter in the hardware design considerations section of the hardcopy series handbook . the hardcopy ii advisor advises on the correct quartus ii settings for timing analysis ( figure 7?4 ). these settings are necessary to ensure you generate accurate and complete timing reports. the list of settings includes the following: enable recovery/removal analysis enable timing constraints check report combined fast/slow timing report i/o paths separately enable clock latency enable misc. timing assignments in the classic timing analysis flow, you must set the value of cut_off_paths_between_clock_domains to off . otherwise, the unconstrained path report (ucp report) will list all clock domain crossing paths as unconstrained. the report do es not honor the on setting, which cuts timing from clocks not originating from the same pll.
7?12 altera corporation september 2008 hardcopy series handbook, volume 1 figure 7?4. classic timing-related set tings in the hardcopy ii advisor classic timing analyzer, unlike the timequest timing analyzer, supports some timing constraints that are incompatible with the hardcopy ii design. in the hardcopy ii advisor, the remove unsupported global timing assignments option and the remove unsupported instance timing assignments option in the check for incompatible assignments list ( figure 7?5 ) together list all the timing constraints that are incompatible wi th the hardcopy ii design flow. these constraints are explained in ?unsupported hard copy ii timing constraints for classic ti ming analyzer? on page 7?21 . although quartus ii successfully comple tes timing analysis if you do not remove these timing constraints, it is very important that you correct all unsupported timing assignments be fore you transfer the hardcopy ii design to the hcdc. failure to remove these incompatible constraints may result in delays during back-end timing closure.
altera corporation 7?13 september 2008 hardcopy ii timing closure methodology figure 7?5. classic timing analyzer unsupport ed timing assignments in hardcopy ii advisor
7?14 altera corporation september 2008 hardcopy series handbook, volume 1 the compilation report for both the stratix ii and hardcopy ii revisions of your project includes a timing constraints check section ( figure 7?6 ). this section reports all un constrained paths based on the coverage provided by the timing co nstraints used in the design. you should examine this report and verify that all internal and i/o paths and all clock domains are constrained for both setup and hold checks. figure 7?6. classic timing analyzer cons traints check in compilation report when using classic timing analyzer, just as when using the timequest timing analyzer, you shou ld review the quartus ii timing report sections in the compilation report and resolve all reported timing violations. constraining timing of hardcopy series devices to ensure that the timing of the hardcopy device meets performance goals, the hardcopy design center ru ns static timing analysis on the design database. for this timing anal ysis to be meaningful, all timing constraints and timing exceptions th at you applied to the design for the fpga implementation, must also be used for the hardcopy implementation. if you di d not use timing constrai nts or you used only partial timing constraints for the design, you must add constraints to
altera corporation 7?15 september 2008 constraining timing of hardcopy series devices make the design fully constrained, an d use the same constraints for both fpga and hardcopy revisions in the flow. if you do not do this, you cannot determine whether the hardcopy series device meets the required timing of the end target system. the sdc format timing constraints can be generated using th e quartus ii sdc file editor which provides line numbering, syntax colo ring, and call tips. you can enter timing constraints and exceptions di rectly or specify them from the constraints menu. an example of the sdc commands is shown in the following section. the following constraints must be included: clock definitions primary input port timing primary output port timing combinational timing timing exceptions f for information on the sdc editor, refer to the timequest timing analyzer chapter in volume 3 of the quartus ii handbook . f for more information on timing co nstraints for the timequest timing analyzer, refer to the timequest timing analyzer chapter in volume 3 of the quartus ii handbook . f for more information on timing assignments for classic timing analyzer, refer to the classic timing analyzer chapter in volume 3 of the quartus ii handbook . clock definitions you can use these definitions to descri be the parameters of all different clock domains in a design. clock para meters that must be defined are frequency, time at which the clock edge rises, time at which the clock edge falls, clock uncertainty (for example: jitter, noise, and de signed in timing margin), and clock name. figure 7?7 illustrates the attributes.
7?16 altera corporation september 2008 hardcopy series handbook, volume 1 figure 7?7. clock attributes the clock settings for pll clocks ar e derived automatically based on the pll settings and reference clock characteristics. you can also override the default pll clock settings for timing analysis by specifying clock settings for the input clock port on the pll. clock uncertainty in pll clock outputs is not modeled by default. you should use the set_clock_uncertainty command to model jitter and any other uncertainty and ma rgin in your pll clocks. 1 consult with your altera field applications engineer (fae) or use mysupport regarding pll cloc k uncertainty calculation for your design. the sdc format provides a simple and easy method to constrain the simplest to the most complex designs. the following example illustrates the simplest sdc commands for a clock (port or pin) and for a generated clock at the pll output pin for a design: #constrain the base clock create_clock -period 10.000 [get_ports clkin] #constrain the pll output clock derive_pll_clocks 1 although derive_pll_clocks is in the sdc_ext package, it is the unique exception to the requirement that all timing constraints in the hardcopy ii design flow must be in the sdc package. this command is auto matically transl ated to the sdc -package command generated_pll_clock prior to transfer to the hcdc. 0.0 clk 5.0 10.0 clock period = 10.0 ns clock uncertainty 0.5 - 0.5 rising edge of clock falling edge of clock
altera corporation 7?17 september 2008 constraining timing of hardcopy series devices f for a full list of available report apis, refer to the sdc and timequest api reference manual . primary input port timing you must specify the primary input port timing constraint for every primary input port in the design (and for the input path of every bidirectional port). the followin g two subsections describe how to constrain input port timing. external input delay specification to constrain the input port timing, describe the external timing environment in terms of the maximum and minimum arrival times of the external signals that drive the primar y input ports of the hardcopy series device or fpga. figure 7?8 shows the external timing constraint that drives the primary input port. the static timing analysis tool can use this external input delay time to check if there is enough time for the data to propagate to the internal nodes of the device. if there is not enough time, a timing violation occurs. figure 7?8. external timing constrai nt driving a primary input port internal input delay specification this approach describes the acceptable maximum on-chip delay for your design. for example, you can use this approach to describe the setup time of a primary input to any register in the design relative to a specific clock. figure 7?9 shows a generic circuit with an on-chip setup-time constraint, which may be different for each clock domain. you may specify the minimum on-chip delay from any prim ary input port to describe input hold-time requirements. external device external input delay primary input to pld/hardcopy series device dq dff dq dff data path delay data path delay hardcopy device or fpga
7?18 altera corporation september 2008 hardcopy series handbook, volume 1 figure 7?9. internal input delay specification (setup) figure 7?10 shows a generic circuit with an on-chip hold-time constraint. figure 7?10. internal input de lay specification (hold) primary output port timing you must specify the output port ti ming constraint for every primary output port in the design and for the output path of every bidirectional port. there are two ways to capture th e output port timing, as described in the following two sections. tsu for a primary input port data clk tsu data path delay clock delay th for a primary input data clk th data path delay clock delay
altera corporation 7?19 september 2008 constraining timing of hardcopy series devices external output delay specification one way to capture output port timing is to describe the external timing environment, which is the maximum and minimum delay times of external signals that are driven by the primary output ports of the hardcopy series device. figure 7?11 shows the external timing constraint driven by the primary outp ut port. the static timing analysis tool uses this informatio n to check that the on-chi p timing of the output signals is within the desired specification. figure 7?11. external timing constraint for a primary output port internal output delay (tco) specification this approach describes the acceptable maximum and minimum on-chip clock-to-output (t co ) delay. for example, you can use this approach to describe the time it takes from the active edge of the clock to the data arriving at the primary output port. figure 7?12 shows a generic circuit with an on-chip t co time constraint. in additi on, there can be a minimum t co requirement. figure 7?12. on-chip clock-to-output (t co ) time constraint dq dff dq dff primary output from fpga/hardcopy series device external device external output delay data path delay data path delay hardcopy device or fpga tco for a primary output port clk data path delay clock delay tco output
7?20 altera corporation september 2008 hardcopy series handbook, volume 1 combinational timing in combinational timing circuits, a pa th exists from a primary input port to a primary output port. this type of circuit does not contain any registers. therefore, it does not require a clock for constraint specification. you only need the maximum and minimum delay from the primary input port to the primary output port to constrain the path for timing requirements. figure 7?13 shows the placement requirement for a combinational delay arc constr aint in a generic circuit. figure 7?13. combinational timing constraint timing exceptions some circuit structures warrant spec ial consideration. for example, you can ignore all timing paths between two clock domains when a design has more than one clock domain and the clock domains are not related. you can ignore all timing paths using the static timing analysis tool by specifying false paths for all signals that go from one clock domain to the other clock domain(s ). additionally, some circ uits are not intended to operate in a single-clock cycle. thes e circuits require that you specify multi-cycle clock exceptions. after capturing the information, the altera hcdc directly checks all timing of the hardcopy series devi ce before tape-out occurs. if any timing violations occur in the hardcopy seri es device due to overly aggressive timing constraints, alte ra must fix them, or you must waive them. input data path delay combinational delay arc output
altera corporation 7?21 september 2008 unsupported hardcopy ii timing constraints for classic timing analyzer unsupported hardcopy ii timing constraints for classic timing analyzer the quartus ii software supports a wide variety of complex timing constraints. when using classic ti ming analyzer for hardcopy ii design, however, some of these cons traints are not translated to sdc format constraints when the design is transferred to the hcdc. the unsupported timing constraints fo r hardcopy ii are listed below: clock enable multicycle paths inverted clocks tsu, th, tco, and min t co internal t pd virtual clocks maximum clock and data skew maximum and minimum delay if these constraints are used, you can still perform timing analysis in the quartus ii software and produce the correct results. however, when a hardcopy ii archive for handoff is created, they will be ignored. the translation of quartus ii timing co nstraints to sdc constraints simply drops unsupported constraints; they do not feed forward to the hcdc. any unsupported constraints in a design are listed under the incompatible assignments section in the hardcopy ii advisor (see figure 7?5 ). while it is possible to translate unsupported constraints to constraints that are supported, the process is difficult and error-prone, often requiring detailed analysis of the particular context in which the constraint is used. for this reason, altera recommends that you use timing constraints in the industry-standard sdc format with the timequest timi ng analyzer or use only supported timing constraints for classic timing analyzer from the start of your hardcopy ii pr oject. this approach avoids any translation or constraint coverage issu es that may occur later in a project and the inevitable delay and risk that results. in some cases, a hardcopy ii proj ect in the quartus ii software may already be using the unsupported cons traints, and you may choose either to translate the existing, unsupported constraints, or re place them with a new set of constraints that use on ly the recommended hardcopy ii timing assignments. in many cases, you may find it easier to rebuild the constraints rather than tr anslate existing constraints. this is because of the ambiguous nature of many unsu pported timing constraints, which often require additional information outside of the quartus ii software before the translation can be prop erly resolved. verifying that the translations produce the same timing constraint coverage and the same timing analysis results can also be a time-consuming and error-prone exercise.
7?22 altera corporation september 2008 hardcopy series handbook, volume 1 if you do wish to translate existing , unsupported timing constraints to recommended constraints, use table 7?1 as a rough guide. it shows how values used in tco, th, tsu, and min t co assignments normally convert to values used in recommended hardcopy ii assignments. in the table, unsupported constraints are listed in the left hand column. recommended constraints are listed al ong the top row. to use the table, cross-reference the unsupported constraints you wish to translate against a recommended constraint. the cr oss reference cell contains the conversion of the original, unsupported constraint value that should be used with the new, recommended constr aint. it is very important to note that these translations are not valid in every design scenario. conclusion this chapter described timing cons iderations and quartus ii timing constraint recommendations for hardcopy ii projects. by understanding these considerations and following th e recommendations in your design, you ensure a smooth transition through the quartus ii software and subsequent transfer to the altera hardcopy design center for the back-end design of your st ructured asic. following the recommendations in this chapter will help ensure success in your hardcopy ii project. table 7?1. tsu, th, tco, and minimum t co timing constraint conversion notes (1) , (2) , (3) , (4) , (5) setup_relationship set_input_delay hold_relationshi p set_output_delay tsu req tsu -max th req -min th -th tco req tco -max min t co req min t co -min <- min t co > note to table 7?1 : (1) tsu = value used in th e tsu requirement assignment. (2) tco = value used in th e tco requirement assignment. (3) th = value used in the th requirement assignment. (4) min t co = value used in min t co requirement assignment. (5) tck = period of the clock for registers a ssociated with the tsu and tco requirements.
altera corporation 7?23 september 2008 document revision history document revision history table 7?2 shows the revision history for this chapter. table 7?2. document revision history date and document version changes made summary of changes september 2008, v2.2 updated chapter number and metadata. ? june 2007, v2.1 minor text edits. ? december 2006 v2.0 major updates for the quartus ii software version 6.1.0 added information on timequest timing analyzer, newly available in quartus ii software version 6.1.0, and recommended for use in hardcopy ii design timing analysis. added ?using the timequest timing analyzer? section. brought in ?constraining timing of hardcopy series devices? section, prev iously in chapter 22. updated ?hardcopy ii timing closure methodology? section. added revision history. a major update to the chapter, due to changes in the quartus ii software version 6.1 release, especially the inclusion of the timequest timing analyzer; most changes were in the ?hardcopy ii timing closure methodology? section, and the addition of the ?using the timequest timing analyzer? and ?constraining timing of hardcopy series devices?sections. march 2006, v1.0 added document to the hardcopy series handbook. ?
7?24 altera corporation september 2008 hardcopy series handbook, volume 1
altera corporation 8?1 september 2008 preliminary 8. migrating stratix ii device resources to hardcopy ii devices introduction altera ? hardcopy ? ii devices and stratix ? ii devices are both manufactured on a 1.2-v, 90-nm process technology and offer many similar features. designers can use the quartus ? ii software to migrate their stratix ii design to a hardcopy ii device. the quartus ii software ensures that the design revision targeting a hardcopy ii device retains the same functionality as the original stratix ii design. beginning with version 5.0 of the qu artus ii software, you can select a hardcopy ii companion device from the device settings dialog box (device menu). selecting a hardcopy ii device as a companion device is similar to adding another stratix ii de vice in the migration device chain. the quartus ii software compiles the design to use the common resources available in all of the selected st ratix ii devices and the selected hardcopy ii devices. the hardcopy ii companion device becomes the target device when you switch to the ha rdcopy ii flow fr om this stratix ii flow later in the quartus ii project compilation. f for more information on compiling with stratix ii and hardcopy ii companion revisions using quartus ii software, refer to the quartus ii support for hardcopy ii devices chapter of the hardcopy series devices handbook . when you select a hardcopy ii companion device, you can set the quartus ii compiler to limit the design to the minimum resource availability of memory blocks and available logic fo r digital signal processing (dsp) from either the targeted stratix ii or hardcopy ii companion device. additional li mitations also include i/o pin assignments and phase-locked loops (plls). this document is a guide for designers migrating stratix ii designs into hardcopy ii devices. this document highlights resources that are not supported by the selected stratix ii and hardcopy ii companion device pair or any resource differences between stratix ii devices and the hardcopy ii device. this document includes the following topics: stratix ii and hardcopy ii migration options i/o support and planning external memory interface support on-chip termination stratix ii and hardcopy ii companion memory blocks pll planning an d utilization h51024-1.4
8?2 altera corporation september 2008 hardcopy series handbook, volume 1 global and local signals stratix ii alm adaptation into hardcopy ii logic hardcopy ii dsp implementati on from stratix ii dsp blocks jtag bst and extended functions power up and configuration compatibility stratix ii and hardcopy ii migration options the quartus ii software allows you to migrate between different stratix ii devices in the same package. when compiling stratix ii designs in the quartus ii software, you can specify one stratix ii target device and one or more stratix ii migration device s. when you specify at least one migration device, the quartus ii compiler constrains the overall design?s i/o pins and other resource assignments to the minimum resources available in any of the selected migr ation devices. this feature allows vertical migration between devices using the same package footprint. to create the proper configuration file for one of the stratix ii devices selected in the migration devices menu , select that device as a target device. the introduction of hardcopy ii provides an additional seamless migration path for stratix ii devices. after you sele ct a particular stratix ii device, the quartus ii software provides migration options in the settings dialog box. for example, if your design targets the ep2s130 device in the 1,020-pin fineline bga ? package, the quartus ii software provides the ep2s90 and ep2s180 devi ces in the 1,020-pin fineline bga package as migration options as well as the HC230 device in the 1,020-pin fineline bga package. conversely, the hardcopy ii architecture allows you to design a structured asic and then prototype with a wide range of stratix ii devices. if the target device is a hardcopy ii hc220 device in the 780-pin fineline bga package, you can sele ct the stratix ii ep2s90 or ep2s130 device in the 780-pin fineline bg a package as proto type devices. table 8?1 shows vertical migration options by package.
altera corporation 8?3 september 2008 preliminary stratix ii and hardcopy ii migration options beginning with version 5.0 of the qu artus ii software, when you compile a design targeting a hardcopy ii device, you will need to select a target stratix ii device and a hardcopy ii companion device for compilation. table 8?2 lists the available hardcopy ii and stratix ii companion pairs. these pairs are retained in most resource availability tables in this chapter to show the maximum resources available that are supported by either device of the companion pair. table 8?1. stratix ii and hardc opy ii migration options note (1) device fineline bga package 484 pins 672 pins 780 pins 1,020 pins 1,020 pins 1,508 pins hardcopy ii hc210 hc220 hc220 HC230 hc240 hc240 stratix ii ep2s30 ep2s60 ep2s90 (2) ep2s60 ep2s90 ep2s130 ep2s90 ep2s130 ep2s180 ep2s180 ep2s180 notes to ta b l e 8 ? 1 : (1) table 8?1 does not include the hc210w device. for information on the hc210w device, contact the altera applications group. (2) this is a hybrid fineline bga package. for more details, refer to the package information for stratix ii devices chapter in volume 2 of the stratix device handbook . table 8?2. stratix ii and hardcopy ii companion devices (part 1 of 2) note (1) package companion pair hardcopy ii device stratix ii device 484-pin fineline bga hc210 ep2s30 484-pin fineline bga hc210 ep2s60 484-pin hybrid fineline bga hc210 ep2s90 (2) 672-pin fineline bga hc220 ep2s60 780-pin fineline bga hc220 ep2s90 780-pin fineline bga hc220 ep2s130 1,020-pin fineline bga HC230 ep2s90 1,020-pin fineline bga HC230 ep2s130
8?4 altera corporation september 2008 hardcopy series handbook, volume 1 when the quartus ii software succ essfully compiles a design, the hardcopy ii device resource guide in the fitter compilation report contains information on migration compatibility to a hardcopy ii device. use this information to select the optimal hardcopy ii device for the prototype stratix ii device based on resource requirem ents and package preference. table 8?3 shows the available resources for prototyping on a stratix ii device when choosing a hardcopy ii device. this chapter examines each resource availability in greater detail. 1,020-pin fineline bga HC230 ep2s180 1,020-pin fineline bga hc240 ep2s180 1,508-pin fineline bga hc240 ep2s180 notes to ta b l e 8 ? 2 : (1) table 8?2 does not include the hc210w devi ce. for information on the hc210w device, contact the altera applications group. (2) this is a hybrid fineline bga package. for more details, refer to the package information for stratix ii devices chapter in volume 2 of the stratix device handbook . table 8?2. stratix ii and hardcopy ii companion devices (part 2 of 2) note (1) package companion pair hardcopy ii device stratix ii device table 8?3. stratix ii and hardcopy ii companion devices resource av ailability guide (part 1 of 2) note (1) stratix ii and hardcopy ii companion devices package stratix ii alms (2) hardcopy ii prototyping resources asic gates for logic user i/o pins (3) m4k blocks m-ram blocks total ram bits 18 18 multipliers plls ep2s30 hc210 484-pin fineline bga 13,552 360k 334 144 0 663,552 64 4 ep2s60 hc210 484-pin fineline bga 24,176 720k 334 190 0 875,520 144 4 ep2s90 hc210 484-pin fineline bga 36,384 1 m 308 190 0 875,520 192 4 ep2s60 hc220 672-pin fineline bga 24,176 720k 492 255 2 2,354,688 144 4 ep2s90 hc220 780-pin fineline bga 36,384 1 m 494 408 2 3,059,712 192 4
altera corporation 8?5 september 2008 preliminary i/o support and planning i/o support and planning hardcopy ii companion devices offe r pin-to-pin compatibility with the stratix ii prototype device, which ma kes them drop-in replacements for the fpgas. therefore, you can use hardcopy ii devices with the same system board and software develope d for prototyping and field trials, enabling the fastest time-to market for high-volume production. hardcopy ii devices offer up to 951 user i/o pins. table 8?4 lists all available i/o pin counts when assi gning a stratix ii device while selecting a hardcopy ii companion device. if a stratix ii design uses i/o pins that are not available in bo th the stratix ii device and the hardcopy ii companion device, the qu artus ii software issues a no-fit error. therefore, it is important to monitor pin assignments based on the stratix ii device and the hardcopy ii companion device. ep2s130 hc220 780-pin fineline bga 53,016 1.6 m 494 408 2 3,059,712 252 4 ep2s90 HC230 1,020-pin fineline bga 36,384 1 m 698 408 4 4,239,360 192 8 ep2s130 HC230 1,020-pin fineline bga 53,016 1.6 m 698 609 6 6,345,216 252 8 ep2s180 HC230 1,020-pin fineline bga 71,760 2.2 m 698 614 6 6,368,256 384 8 ep2s180 hc240 1,020-pin fineline bga 71,760 2.2 m 742 768 (4) 9 8,847,360 384 12 ep2s180 hc240 1,508-pin fineline bga 71,760 2.2 m 951 768 (4) 9 8,847,360 384 12 notes to ta b l e 8 ? 3 : (1) table 8?3 does not include the hc210w device. for information on the hc210w device, contact the altera applications group. (2) alm: adaptive logic module. (3) user i/o pin counts are preliminary. the quartus ii software i/o pin counts include one additional pin, pll_ena , which is not included in this pin count. (4) the total number of usable m4k blocks is limited to 768 to allow migration compatib ility when prot otyping with an ep2s180 device. table 8?3. stratix ii and hardcopy ii companion devices resource av ailability guide (part 2 of 2) note (1) stratix ii and hardcopy ii companion devices package stratix ii alms (2) hardcopy ii prototyping resources asic gates for logic user i/o pins (3) m4k blocks m-ram blocks total ram bits 18 18 multipliers plls
8?6 altera corporation september 2008 hardcopy series handbook, volume 1 hardcopy ii devices offer three dist inct types of i/o elements (ioes) which support a variety of i/o features to match stratix ii ioes. these are memory interface ioes, high-speed ioes, and general purpose ioes. memory interface ioes su pport popular i/o standa rds used by external memory devices, including single-ended standards from lvttl, lvcmos to sstl, and hstl voltage referenced (v ref ) type i/o standards. memory interface ioes also have pci clamp circuitry for pci support. high-speed ioes support differential applications utilizing lvds and hypertransport technology . high-speed ioes also support single-ended lvttl and lvcmos i/o standards, but do not support v ref i/o standards. general purpose ioes support lvttl and lvcmos i/o standards. general purpose ioes on the bottom i/ o banks (banks 7 and 8) also have pci clamping circuitry to support th e pci interface on hardcopy ii devices. table 8?4. package options and i/o pin counts for stratix ii and hardcopy ii companion devices notes (1) , (2) stratix ii device hc210 hc220 HC230 (3) hc240 (4) 484-pin fineline bga 672-pin fineline bga 780-pin fineline bga 1,020-pin fineline bga 1,020-pin fineline bga 1,508-pin fineline bga ep2s30 334 ep2s60 334 492 ep2s90 308 494 698 ep2s130 494 698 ep2s180 698 742 951 notes to ta b l e 8 ? 4 : (1) user i/o pin counts are preliminary. the quartus ii software i/o pin counts include one additional pin, pll_ena , which is not included in this pin count. the pll_ena pin is not available as a general purpose i/o pin and can only be used to enable the plls in this device. (2) all i/o pin counts include ei ght dedicated clock input pins ( clk1p , clk1n , clk3p , clk3n , clk9p , clk9n , clk11p , and clk11n ) that can be used for data inputs. (3) the i/o pin counts for all HC230 combinations include four dedicated fast pll clock inputs ( fpll7clkp/n , fpll8clkp/n ) that can be used for data inputs. (4) the i/o pin counts for hc240 combinations in clude eight dedicated fast pll clock inputs ( fpll7clkp/n , fpll8clkp/n , fpll9clkp/n , and fpll10clkp/n ) that can be used for data inputs.
altera corporation 8?7 september 2008 preliminary i/o support and planning f for more information on hard copy ii ioes, refer to the hardcopy ii description, architecture, and features chapter of the hardcopy series handbook . hardcopy ii i/o banks hardcopy ii devices have eight general i/o banks and up to four enhanced pll external clock output banks (banks 9, 10, 11, 12). hc210 and hc220 devices only have pll output banks 9 and 10. figure 8?1 shows the hardcopy ii i/o banks and the relative pll positions. the left side i/o banks 1 and 2 are high speed ioe banks on all hardcopy ii devices. the right side i/o banks 5 and 6 are general purpose ioes on hc210, hc220, and HC230 devices, but high speed ioes on hc240 devices. the top i/o banks 3 and 4 are memory interface ioes on all hardcopy ii devices. the bottom i/o banks 7 an d 8 are general purpose ioes on hc210 and hc220 but memory in terface ioes on HC230 and hc240 devices. the general purpose ioes on the bottom of the device support pci clamping, but the general purpos e ioes on the right side do not.
8?8 altera corporation september 2008 hardcopy series handbook, volume 1 figure 8?1. hardcopy ii hc240 i/o banks notes (1) , (2) , (3) , (4) notes to figure 8?1 : (1) figure 8?1 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. it is a graphical representation only. refer to the pin list and quartus ii software for exact locations. (2) differential hstl and differential sstl standards are av ailable for bidirectional oper ations on dqs pin and input only operations on pll clock input pi ns; lvds, lvpecl, and hypertransport st andards are available for input only operations on pll clock input pins. refer to ?differential i/o termination? on page 8?20 for more details. (3) hardcopy ii devices and the quartus ii software does not support differential sstl and differential hstl standards at left and right i/o banks. side i/o banks do not have v ref pins. (4) figure 8?1 shows the hc240 device. other hardco py ii devices have fewer pll blocks. bank 4 memory interface ioes bank 7 memory interface ioes bank 8 memory interface ioes i/o banks 3 & 4 support 3.3-v, 2.5-v, 1. 8 -v lvttl/ lvcmos, 1.5-v lvcmos, sstl-2, sstl-1 8 , 1. 8 -v hstl, 1.5-v hstl & pci/pci-x i/o standards. i/o banks 7 & 8 support 3.3-v, 2.5-v, 1. 8 -v lvttl/ lvcmos, 1.5-v lvcmos & pci/pci-x i/o standards. bank 3 memory interface ioes bank 2 high-speed ioes bank 1 high-speed ioes bank 5 high-speed ioe s bank 6 high-speed ioe s pll 1 pll 2 pll 4 pll 3 i/o banks 5 & 6 support 3.3-, 2.5- & 1. 8 -v lvttl/lvcmos, 1.5-v lvcmos, lvds & hypertransport technology i/o banks 1 & 2 support 3.3-, 2.5- & 1. 8 -v lvttl/lvcmos, 1.5-v lvcmos, lvds & hypertransport technology clk, pll_fb input pins & pll_out output pins support differential sstl, differential hstl, lvds & hypertransport technology. clk & pll_fb pins support lvpecl. dqs input pins support differential sstl and differential hstl i/o standards. clk, pll_fb input pins sstl-2, sstl-1 8 , 1. 8 -v hstl, 1.5-v hst, & pll_out output pins support differential sstl, differential hstl, lvds & hypertransport technology. clk & pll_fb pins support lvpecl. dqs input pins support differential sstl and differential hstl i/o standards. pll 5 pll 11 bank 11 bank 9 pll 6 pll 12 bank 12 bank 10 pll 10 pll 9 pll 7 pll 8
altera corporation 8?9 september 2008 preliminary i/o support and planning user i/o count per ioe type and bank location table 8?5 lists the maximum i/o count per ioe type. this helps you select a hardcopy ii device based on the i/o standard support requirement. hardcopy ii supported i/o standards table 8?6 lists i/o standards that ha rdcopy ii devices supports, separated by ioe type. this list only focuses on user i/o pins. table 8?5. hardcopy ii maximum user i/o count per ioe type notes (1) , (2) device package memory interface ioes general purpose ioes high-speed ioes top bottom right bottom left right hc210 484-pin fineline bga 87 84 79 84 hc220 672-pin fineline bga 126 124 118 124 hc220 780-pin fineline bga 126 124 120 124 HC230 (3) 1,020-pin fineline bga 180 178 152 188 hc240 (4) 1,020-pin fineline bga 184 182 188 188 hc240 (4) 1,508-pin fineline bga 238 233 240 240 notes to ta b l e 8 ? 5 : (1) user i/o pin counts are preliminar y. the quartus ii software i/o pin co unts include one additional pin, pll_ena , which is not included in this pin count. the pll_ena pin is not available as a general purpose i/o pin and can only be used to enable the plls in this device. (2) all i/o pin counts include ei ght dedicated clock input pins ( clk1p , clk1n , clk3p , clk3n , clk9p , clk9n , clk11p , and clk11n ) that can be used for data inputs. (3) the i/o pin counts for all HC230 combinations include four dedicated fast pll clock inputs ( fpll7clkp/n , fpll8clkp/n ) that can be used for data inputs. (4) the i/o pin counts for hc240 combinations in clude eight dedicated fast pll clock inputs ( fpll7clkp/n , fpll8clkp/n , fpll9clkp/n , and fpll10clkp/n ) that can be used for data inputs. table 8?6. hardcopy ii supported i/o st andards on user i/o pins (part 1 of 2) i/o standard type v ccio level (v) memory interface ioes general purpose ioes high- speed ioes input output 3.3-v lvttl/lvcmos single-ended 3.3/2.5 3.3 vvv 2.5-v lvttl/lvcmos single-ended 3.3/2.5 2.5 vvv 1.8-v lvttl/lvcmos single-ended 1.8/1.5 1.8 vvv 1.5-v lvcmos single-ended 1.8/1.5 1.5 vvv
8?10 altera corporation september 2008 hardcopy series handbook, volume 1 sstl-2 class i and ii voltage referenced 2.5 2.5 v sstl-18 class i and ii voltage referenced 1.8 1.8 v 1.8-v hstl class i and ii voltage referenced 1.8 1.8 v 1.5-v hstl class i and ii voltage referenced 1.5 1.5 v pci / pci-x single-ended 3.3 3.3 v (1) differential sstl-2 class i and ii input pseudo differential (3) 3.3/2.5/ 1.8/1.5 (2) differential sstl-2 class i and ii output pseudo differential (3) 2.5 (2) differential sstl-18 class i and ii input pseudo differential (3) 3.3/2.5/ 1.8/1.5 (2) differential sstl-18 class i and ii output pseudo differential (3) 1.8 (2) 1.8-v differential hstl class i and ii input pseudo differential (3) 3.3/2.5/ 1.8/1.5 1.8/1.5 (2) 1.8-v differential hstl class i and ii output pseudo differential (3) 1.8 (2) 1.5-v differential hstl class i and ii input pseudo differential (3) 3.3/2.5/ 1.8/1.5 (2) 1.5-v differential hstl class i and ii output pseudo differential (3) 1.5 (2) lvds differential 2.5 2.5 v hypertransport? technology differential 2.5 2.5 v notes to ta b l e 8 ? 6 : (1) like stratix ii devices, the optional pci clamp is only available on column i/o pins. general purpose ioes on the right row i/o pins do not support the pci clamp. (2) similar to stratix ii devices, these i/o standards are only available on input clock pins , output clock pins in i/o banks 9, 10, 11, 12, and dqs pins in top i/o banks 3, 4 for all hardcopy ii devices, and dqs pins in bottom i/o banks 7 and 8 for HC230 and hc240 devices. (3) pseudo-differential hstl and sstl inputs only use the positive polarity input in the speed path. the negative input is not connected internally. pseudo-differential hs tl and sstl outputs use two single-ended outputs with the second output programmed as inverted. this is similar to a stratix ii device implementation. table 8?6. hardcopy ii supported i/o st andards on user i/o pins (part 2 of 2) i/o standard type v ccio level (v) memory interface ioes general purpose ioes high- speed ioes input output
altera corporation 8?11 september 2008 preliminary i/o support and planning table 8?7 lists the i/o standards that hardcopy ii devices support. table 8?7 is organized by clock input, clock output, and pll feedback pins. table 8?7. hardcopy ii supported i/o standards of input clocks, cloc k out, and pll feedback (part 1 of 2) i/o standard type v ccio level (v) clk[0..3, 8..11] (1) clk[4..7, 12..15] (2) fpll_clk (3) pll_out (4) pll_fb (5) input output 3.3-v lvttl / lvcmos single- ended 3.3/2.5 3.3 vvvvv 2.5-v lvttl / lvcmos single- ended 3.3/2.5 2.5 vvvvv 1.8-v lvttl / lvcmos single- ended 1.8/1.5 1.8 vvvvv 1.5-v lvcmos single- ended 1.8/1.5 1.5 vvvvv sstl-2 class i voltage referenced 2.5 2.5 vvv sstl-2 class ii voltage referenced 2.5 2.5 vvv sstl-18 class i voltage referenced 1.8 1.8 vvv sstl-18 class ii voltage referenced 1.8 1.8 vvv 1.8-v hstl class i voltage referenced 1.8 1.8 vvv 1.8-v hstl class ii voltage referenced 1.8 1.8 vvv 1.5-v hstl class i voltage referenced 1.5 1.5 vvv 1.5-v hstl class ii voltage referenced 1.5 1.5 vvv pci / pci-x single- ended 3.3 3.3 vvv differential sstl-2 class i and ii input pseudo differential (6) 3.3/2.5/ 1.8/1.5 vv differential sstl-2 class i and ii output pseudo differential (6) 2.5 vv differential sstl-18 class i and ii input pseudo differential (6) 3.3/2.5/ 1.8/1.5 vv
8?12 altera corporation september 2008 hardcopy series handbook, volume 1 differential sstl-18 class i and ii output pseudo differential (6) 1.8 vv 1.8-v differential hstl class i and ii input pseudo differential (6) 3.3/2.5/ 1.8/1.5 vv 1.8-v differential hstl class i and ii output pseudo differential (6) 1.8 vv 1.5-v differential hstl class i and ii input pseudo differential (6) 3.3/2.5/ 1.8/1.5 vv 1.5-v differential hstl class i and ii output pseudo differential (6) 1.5 vv lvds input differential 2.5 vvv v lvds output differential 2.5 vv hypertransport technology input differential 2.5 vvv v hypertransport technology output differential 2.5v vv lvpecl input differential 3.3/2.5/ 1.8/1.5 (7) vvv notes to ta b l e 8 ? 7 : (1) clk8 and clk10 pins on hc210, hc220, and HC230 devices do not support differential standards lvds and hypertransport technology. only lvttl is supported on these clk pins for these devices. (2) clk[4..7] pins on hc210 and hc220 devices do not support sstl, hstl, differential sstl, and hstl input or output. (3) HC230 only has two fast pll clocks, fpll[7..8]clk . hc240 has four fpll clocks, fpll[7..10]clk . (4) hc210 and hc220 pll6_out pins do not support sstl, hstl, differential sstl, and hstl input or output. (5) hc210 and hc220 pll6_fb pins do not support sstl, hstl, differ ential sstl, and hstl input or output. (6) pseudo-differential hstl and sstl inputs only use the positive polarity input in the speed path. the negative input is not connected internally. pse udo-differential hstl and sstl outputs use two single-ended outputs with the second output programmed as inverted. this is similar to a stratix ii device implementation. (7) this is not supported. table 8?7. hardcopy ii supported i/o standards of input clocks, cloc k out, and pll feedback (part 2 of 2) i/o standard type v ccio level (v) clk[0..3, 8..11] (1) clk[4..7, 12..15] (2) fpll_clk (3) pll_out (4) pll_fb (5) input output
altera corporation 8?13 september 2008 preliminary external memory interface support external memory interface support like stratix ii devices, hardcopy ii i/o pins have dedicated phase-shift circuitry for interfacing with exte rnal memory, including ddr and ddr2 sdram, qdr ii sram, rldram ii , and sdr sdram. a compensated delay element on each dqs pin automatically aligns input dqs synchronization signals wi th the data window of their corresponding dq data signals. for all hardcopy ii devices, the top i/o banks (3 and 4) support dq and dqs signals with dq bus modes that vary from 4, 8/9, 16/18 and up to 32/36. the top bank has a phase-shifting reference circuit that controls the compensated delay elements for all dqs pins on the top bank. for the HC230 and hc240 hardcopy ii devices, the bottom i/o banks (7 and 8) also support dq and dqs signals with dq bus modes from 4, 8/9, 16/18 and 32/36. simila r to the top banks, the bottom i/o banks of these devices also have a phase-shifting reference circuit to control the delay elements at the bottom dqs pins. table 8?8 shows the number of dq and dqs buses supported per companion device pair. (3) table 8?8. dq and dqs bus mode support for stratix ii and hardcopy ii companion devices (part 1 of 2) note (1) stratix ii and hardcopy ii companion devices package number of 4 groups number of 8/9 groups number of 16/18 groups number of 32/36 groups ep2s30 hc210 (2) 484-pin fineline bga 4 2 ep2s60 hc210 (2) 484-pin fineline bga 4 2 ep2s90 hc210 (2) 484-pin fineline bga 4 2 ep2s60 hc220 (2) 672-pin fineline bga 9 4 2 ep2s90 hc220 (2) 780-pin fineline bga 9 4 2 ep2s130 hc220 (2) 780-pin fineline bga 9 4 2 ep2s90 HC230 (3) 1,020-pin fineline bga 36 18 8 4 ep2s130 HC230 (3) 1,020-pin fineline bga 36 18 8 4
8?14 altera corporation september 2008 hardcopy series handbook, volume 1 lvds, serdes, and dpa compatibility hardcopy ii devices offer up to 116 transmitter and receiver pairs. similar to stratix ii devices, these diff erential i/o pins are located on row i/o pins. the hc240 device?s left an d right banks are high-speed ioes which support differential transm ission. the hc210, hc220, and HC230 devices only support differential transmission on the left banks. the lvds and hypertransport technology interface functionality, including the serdes and dpa, is the same as stratix ii devices. table 8?9 shows the maximum differential channel supported by each hardcopy ii and stratix ii companion pair. ep2s180 HC230 (3) 1,020-pin fineline bga 36 18 8 4 ep2s180 hc240 1,020-pin fineline bga 36 18 8 4 ep2s180 hc240 1,508-pin fineline bga 36 18 8 4 notes to ta b l e 8 ? 8 : (1) the dq and dqs numbers are preliminary. (2) hardcopy ii devices hc210 and hc220 support memory inte rface in the top i/o banks only. unlike their stratix ii companions, these devices cannot support dimms. (3) similar to their stratix ii companions, these device and package combinations can support two 64- or 72-bit dimms in 4 and 8/9 modes. table 8?8. dq and dqs bus mode support for stratix ii and hardcopy ii companion devices (part 2 of 2) note (1) stratix ii and hardcopy ii companion devices package number of 4 groups number of 8/9 groups number of 16/18 groups number of 32/36 groups table 8?9. differential channels with stratix ii and hardcopy ii companion devices (part 1 of 2) note (1) stratix ii and hardcopy ii companion devices package transmitters receivers ep2s30 hc210 (2) 484-pin fineline bga 19 21 ep2s60 hc210 (2) 484-pin fineline bga 19 21 ep2s90 hc210 (2) 484-pin fineline bga 19 21
altera corporation 8?15 september 2008 preliminary external memory interface support programmable drive strength support the maximum current strength setting is the default setting in the quartus ii software and achieves ma ximum i/o performance. stratix ii device output buffers for each i /o pin have a programmable drive strength control for certain i/o standards. hardcopy ii support for these settings differs from that found in stratix ii devices. for compatibility with ha rdcopy ii hc210 and hc220 devices, you must restrict the i/o drive settings of stratix ii companion devices, as shown in table 8?10 . ep2s60 hc220 (2) 672-pin fineline bga 29 31 ep2s90 hc220 (2) 780-pin fineline bga 29 31 ep2s130 hc220 (2) 780-pin fineline bga 29 31 ep2s90 HC230 (2) 1,020-pin fineline bga 44 46 ep2s130 HC230 (2) 1,020-pin fineline bga 44 46 ep2s180 HC230 (2) 1,020-pin fineline bga 44 46 ep2s180 hc240 (3) 1,020-pin fineline bga 88 92 ep2s180 hc240 (3) 1,508-pin fineline bga 116 116 notes to ta b l e 8 ? 9 : (1) pin count does not include dedi cated pll input and output pins. (2) the total number of receiver channels for hc210, hc220, and HC230 devices include two non-dedicated clock channels that can optionally be used as data channels. (3) the total number of receiver chan nels for hc240 devices include four non-dedicated clock channels that can op tionally be used as data channels. table 8?9. differential channels with stratix ii and hardcopy ii companion devices (part 2 of 2) note (1) stratix ii and hardcopy ii companion devices package transmitters receivers
8?16 altera corporation september 2008 hardcopy series handbook, volume 1 table 8?10. hc210 and hc220 device programmable drive strengths i/o standard i oh and i ol current strength setting (ma) for top column i/o pins i oh and i ol current strength setting (ma) for bottom column i/o pins i oh and i ol current strength setting (ma) for left row i/o pins i oh and i ol current strength setting (ma) for right row i/o pins 3.3-v lvttl 24, 20, 12, 8, 4 (1) 12, 8, 4 (1) 12, 8, 4 12, 8, 4 3.3-v lvcmos 24, 20, 12, 8, 4 (1) 8, 4 (1) 8, 4 8, 4 2.5-v lvttl/lvcmos 16, 12, 8, 4 12, 8, 4 (1) 12, 8, 4 12, 8, 4 1.8-v lvttl/lvcmos 12, 10, 8, 6, 4, 2 8, 6, 4, 2 (1) 8, 6, 4, 2 8, 6, 4, 2 1.5-v lvcmos 8, 6, 4, 2 4, 2 (1) 4, 2 4, 2 sstl-2 class i 12, 8 (2) (3) (3) sstl-2 class ii 24, 20, 16 (2) (3) (3) sstl-18 class i 12, 10, 8, 6, 4 (2) (3) (3) sstl-18 class ii 20, 18, 16, 8 (2) - - hstl-18 class i 12, 10, 8, 6, 4 (2) - - hstl-18 class ii 20, 18, 16 (2) - - hstl-15 class i 12, 10, 8, 6, 4 (2) - - hstl-15 class ii 20, 18, 16 (2) - - notes to table 8?10 : (1) hardcopy ii devices do not support so me of the settings available in the stratix ii prototype device. for more information, refer to the stratix ii device family data sheet in volume 1 of the stratix ii device handbook . (2) hc220 and hc210 devices do not support memo ry interface standards on bottom i/o pins. (3) row i/o pins do not support sstl i/o standards.
altera corporation 8?17 september 2008 preliminary on-chip termination similarly, when using hardcopy ii HC230 and hc240 devices as companion devices, you must restrict the i/o drive settings, as shown in table 8?11 . on-chip termination like stratix ii devices, hardcopy ii devices feature on-chip termination (oct) to provide i/o impedance matching and termination capabilities. to maintain compatibility with stra tix ii prototype devices, hardcopy ii devices support on-chip series term ination (rs) for single-ended i/o standards and on-chip differential te rmination (rd) for differential i/o standards. however, some hardcopy ii pins do not support the on-chip termination that may be available on the same stratix ii pin. this section highlights the terminat ion schemes that hardcopy ii devices support. table 8?11. HC230 and hc240 device programmable drive strengths i/o standard i oh and i ol current strength setting (ma) for column i/o pins i oh and i ol current strength setting (ma) for row i/o pins 3.3-v lvttl 24, 20, 16, 12, 8, 4 (1) 12, 8, 4 3.3-v lvcmos 24, 20, 16, 12, 8, 4 (1) 8, 4 2.5-v lvttl/lvcmos 16, 12, 8, 4 12, 8, 4 1.8-v lvttl/lvcmos 12, 10, 8, 6, 4, 2 8, 6, 4, 2 1.5-v lvcmos 8, 6, 4, 2 4, 2 sstl-2 class i 12, 8 (2) sstl-2 class ii 24, 20, 16 (2) sstl-18 class i 12, 10, 8, 6, 4 (2) sstl-18 class ii 20, 18, 16, 8 - hstl-18 class i 12, 10, 8, 6, 4 - hstl-18 class ii 20, 18, 16 - hstl-15 class i 12, 10, 8, 6, 4 - hstl-15 class ii 20, 18, 16 - notes to ta b l e 8 ? 11 : (1) hardcopy ii devices do not support some of the settings available in the stratix ii prototype device. for more information, refer to the stratix ii device family data sheet in volume 1 of the stratix ii device handbook . (2) row i/o pins do not su pport sstl i/ o standards.
8?18 altera corporation september 2008 hardcopy series handbook, volume 1 on-chip series termination stratix ii and hardcopy ii devices su pport i/o driver on-chip series termination (rs) through drive-stre ngth control for single-ended i/o standards. there are two ways to implement the rs in stratix ii and hardcopy ii devices: rs without calibration for both row and column i/o pins rs with calibration only for column i/o pins on-chip series termina tion without calibration hardcopy ii devices support outp ut-driver impedance matching to closely match the impedance of the transmission line. if you select matching impedance, you cannot select programmable-current drive strength. table 8?12 lists the hardcopy ii HC230 and hc240 output standards that support on-chip seri es termination without calibration. table 8?12. HC230 and hc240 selectable i/o drivers with on-chip series termination without calibration note (1) i/o standard column i/ o pins row i/o pins 3.3-v lvttl 25 or 50 25 or 50 3.3-v lvcmos 25 or 50 25 or 50 2.5-v lvttl 25 or 50 25 or 50 2.5-v lvcmos 25 or 50 25 or 50 1.8-v lvttl 25 or 50 50 1.8-v lvcmos 25 or 50 50 1.5-v lvttl 50 1.5-v lvcmos 50 2.5-v sstl class i 50 (2) 2.5-v sstl class ii 25 (2) 1.8-v sstl class i 50 (2) 1.8-v sstl class ii 25 1.8-v hstl class i 50 (2) 1.8-v hstl class ii 25 1.5-v hstl class i (3) notes to ta b l e 8 ? 1 2 : (1) these numbers are preliminary an d pending silicon characterization. (2) hardcopy ii HC230 and hc240 devices do not support on-chip series termination with this i/o standard on these pins. (3) support pending hardcopy ii characterization.
altera corporation 8?19 september 2008 preliminary on-chip termination table 8?13 lists the hardcopy ii hc210 and hc220 output standards that support on-chip series term ination without calibration. on-chip series termin ation with calibration stratix ii devices support on-chip series termination with calibration in column i/o pins in the top and bo ttom banks. HC230 and hc240 devices also support on-chip series termination with calibration in column i/o pins in the top and bottom banks, but hc220 and hc210 devices only support this feature on the top i/o banks. table 8?14 lists available i/o standards on the hardcopy ii device s that support calibrated-series termination. table 8?13. hc210 and hc220 selectable i/o drivers with on -chip series terminati on without calibration note (1) i/o standard top column i/o pins bottom column i/o pins left row i/o pins right row i/o pins 3.3-v lvttl 25 or 50 25 or 50 25 or 50 25 or 50 3.3-v lvcmos 25 or 50 25 or 50 25 or 50 25 or 50 2.5-v lvttl 25 or 50 25 or 50 25 or 50 25 or 50 2.5-v lvcmos 25 or 50 25 or 50 25 or 50 25 or 50 1.8-v lvttl 25 or 50 50 50 50 1.8-v lvcmos 25 or 50 50 50 50 1.5-v lvttl (3) (2) 1.5-v lvcmos (3) (2) 2.5-v sstl class i 50 (2) (2) (2) 2.5-v sstl class ii 25 (2) (2) (2) 1.8-v sstl class i 50 (2) (2) (2) 1.8-v sstl class ii 25 (2) 1.8-v hstl class i 50 (2) (2) (2) 1.8-v hstl class ii 25 (2) 1.5-v hstl class i (3) (2) notes to table 8?13 : (1) all these numbers are preliminary and pending silicon characterization. (2) hardcopy ii hc210 and hc220 devices do not support on-c hip series termination with this i/o standard on these pins. (3) support pending hardcopy ii characterization.
8?20 altera corporation september 2008 hardcopy series handbook, volume 1 differential i/o termination similar to the fpga, hardcopy ii devices provide an on-chip 100- differential termination option on ea ch differential receiver channel for lvds and hypertransport technology standards. when using an hc240 device as a companion device, differential termination is supported on all row i/o pins that support lvds and hypertransport technology standards. when using HC230, hc220, and hc210 de vices, only the left row i/o pins support differential terminatio n. the right row i/o pins do not support lvds and hypertrans port technology standards. table 8?14. hardcopy ii selectable i/ o drivers with on-chip series termination with calibration note (1) i/o standard HC230, hc240 column i/o pins hc210, hc220 top column i/o pins (2) 3.3-v lvttl 25 or 50 25 or 50 3.3-v lvcmos 25 or 50 25 or 50 2.5-v lvttl 25 or 50 25 or 50 2.5-v lvcmos 25 or 50 25 or 50 1.8-v lvttl 25 or 50 25 or 50 1.8-v lvcmos 25 or 50 25 or 50 1.5-v lvttl (3) 50 1.5-v lvcmos (3) 50 2.5-v sstl class i 50 50 2.5-v sstl class ii 25 50 1.8-v sstl class i 50 50 1.8-v sstl class ii 25 25 1.8-v hstl class i 50 50 1.8-v hstl class ii 25 25 1.5-v hstl class i (3) 50 notes to ta b l e 8 ? 1 4 : (1) these numbers are preliminary an d pending silicon characterization. (2) hardcopy ii hc210 and hc220 devices do not support on-chip series termination with calibratio n on bottom i/o pins. (3) support pending hardcopy ii characterization.
altera corporation 8?21 september 2008 preliminary stratix ii and hardcopy ii companion memory blocks table 8?15 shows the differential termination support. stratix ii and hardcopy ii companion memory blocks hardcopy ii device ram bit offering s range from 663 kbits to 8.8 mbits. hardcopy ii memory blocks are func tionally equivalent to the stratix ii memory blocks. hardcopy ii memory blocks can implement various stratix ii device memory configurations, including simple and true dual port modes, fifo, parity bits, rom modes, and all other features, as listed in the hardcopy ii description, architecture, and features chapter of the hardcopy series handbook . one difference between hardcopy ii and stratix ii devices is that hardcopy ii devices do not support m512 blocks. additionally, you cannot pre-load hardcopy ii m4k blocks with a memory initialization file ( .mif ) when used as ram. table 8?16 shows all the memory block of ferings when compiling for a stratix ii fpga in conjunction with a hardcopy ii companion device. use table 8?16 as a guide when optimizing memory requirements for selected stratix ii and hardcopy ii pairs. table 8?15. hardcopy ii i/o banks supporting 100- differential termination notes (1) , (2) i/o standard hc240 left and right banks (1, 2, 5 and 6) hc240 top and bottom banks (3, 4, 7 through 12) HC230, hc210, hc220 left banks (1 and 2) HC230, hc210, hc220 other banks (3 to 12) lvds vv hypertransport technology vv clock inputs (3) vv notes to table 8?15 : (1) HC230, hc220, and hc210 device left clock pins clk0 and clk2 support differential on-chip termination. (2) all other clock pins, including fpll[7..10]clk, do not support differe ntial on-chip termination. (3) hardcopy ii hc240 device clock pins clk0 , clk2 , clk8 , and clk10 support differential on-chip termination, similar to stratix ii devices. table 8?16. total ram blocks for stratix ii and hardcopy ii companion devices (part 1 of 2) stratix ii and hardcopy ii companion devices package m4k blocks m-ram blocks total ram bits ep2s30 hc210 484-pin fineline bga 144 0 663,552 ep2s60 hc210 484-pin fineline bga 190 0 875,520
8?22 altera corporation september 2008 hardcopy series handbook, volume 1 table 8?16 does not list m512 blocks because they are not supported in hardcopy ii devices. also, the hc210 devices do not offer m-ram blocks. some compatibility guidelines are discussed in the next sections. m512 options hardcopy ii devices do not support m512 blocks. when compiling stratix ii designs with hardcopy ii companions devices in the quartus ii software, you must check the limit dsp and ram to hardcopy ii resources box in the device settings dialog box (assignments menu). this automatically places all memory blocks in the available hardcopy ii resources. if you do not check this box, the quartus ii software may use memory resources not available in the hardcopy ii device but available in the stratix ii device, such as m5 12 blocks. however, migration into hardcopy ii devices is not allowed and this is indicated in the quartus ii fitter report. ep2s90 hc210 484-pin fineline bga 190 0 875,520 ep2s60 hc220 672-pin fineline bga 255 2 2,354,688 ep2s90 hc220 780-pin fineline bga 408 2 3,059,712 ep2s130 hc220 780-pin fineline bga 408 2 3,059,712 ep2s90 HC230 1,020-pin fineline bga 408 4 4,239,360 ep2s130 HC230 1,020-pin fineline bga 609 6 6,345,216 ep2s180 HC230 1,020-pin fineline bga 614 6 6,368,256 ep2s180 hc240 1,020-pin fineline bga 768 (1) 9 8,847,360 ep2s180 hc240 1,508-pin fineline bga 768 (1) 9 8,847,360 note to table 8?16 (1) the total number of usable m4k blocks is limited to 768 to allow migration compatibility when prototypin g with an ep2s180 device. table 8?16. total ram blocks for stratix ii and hardcopy ii companion devices (part 2 of 2) stratix ii and hardcopy ii companion devices package m4k blocks m-ram blocks total ram bits
altera corporation 8?23 september 2008 preliminary stratix ii and hardcopy ii companion memory blocks your hardcopy ii design can use m4k memory blocks to implement memory designs instead of m512 bloc ks. quartus ii megafunctions offer various memory implementations that use m4k blocks. when using the quartus ii megawizard ? plug-in manager to configure the megafunction, altera recommends selecting the auto option to allow the quartus ii software to determine how the design is implemented in the memory blocks ( figure 8?2 ). this allows the quartus ii software to optimize memory selection based on memory size and placement requirements into the available me mory blocks of the selected hardcopy ii and stratix ii companion pair. figure 8?2. quartus ii megafunction ram selection you can select logic cells in the megafunction to implement small-memory blocks in your desi gn. this implements the memory design in stratix ii alms or hardco py ii hcells. however, there may be power and performance trade-offs when choosing between an m4k or m-ram block or using the alms (or hcells). hardcopy ii devices power down unused m4k blocks, m-ram bl ocks, and hcells. 1 implementing memory blocks us ing logic cells, as seen in figure 8?2 , allows you to select a memory implementation functionally equivalent to m512 blocks or a non-equivalent option to save resources. altera recommends setting the option to a functionally equivalent version with the m512 blocks. for very small memory implementati ons such as a 8 16 single port ram, the m4k or m-ram blocks will be under-utilized, and may be less power efficient than a small number of hcells. if you select the logic cell option, only a fraction of alms are re quired in the stratix ii device, which translates into a small number hcells used in the hardcopy ii device. however, when performance is a key factor, or your design requires alms to implement other logic, it may be more efficient to use m4k blocks. altera recommen ds using the quartus ii software to analyze performance trade-offs be tween the given options.
8?24 altera corporation september 2008 hardcopy series handbook, volume 1 m4k utilization hardcopy ii m4k block functionality is similar to stratix ii m4k blocks. you cannot pre-load hardcopy ii m4k blocks with a memory initialization file ( .mif ) when used as ram. also, unlike stratix ii devices, the hardcopy ii m4k ram contents and their output registers are unknown after power up. however, if the hardcopy ii m4k block is designated as rom, it powers up with the rom contents. when designing m4k blocks as ram, altera recommends writing to the block before reading from it to avoid reading unknown initial power-up data conditions. one advantage over stra tix ii ram blocks is unused m4k blocks are disconnected from the powe r rails, optimizing overall power consumption. m-ram compatibility hardcopy ii m-ram blocks share the same functionality as stratix ii m-ram blocks. one key feature with hardcopy ii m-ram blocks is power optimization when the m-ram block is not used. unused m-ram blocks are disconnected from the powe r rails, optimizing overall power consumption. 1 some stratix ii devices (engineering sample devices and revision a production devices) have m-ram functionality that differs slightly from current stratix ii production devices. hardcopy ii m-ram functionality only matches that of current stratix ii devices. hence, in order to maintain proper compatibility, compiling only fo r current production stratix ii devices is supported. more info rmation on the stratix ii m-ram errata can be found in the stratix ii fpga family errata sheet available on the altera website ( www.altera.com ) .
altera corporation 8?25 september 2008 preliminary stratix ii and hardcopy ii companion memory blocks table 8?17 lists the m4k and m-ram bloc k supported fe atures. this information can also be found in the hardcopy ii description, architecture, and features chapter of the hardcopy series handbook . table 8?17. hardcopy ii embedded memory features (part 1 of 2) feature m4k blocks m-ram blocks total ram bits (including parity bits) 4,608 589,824 configurations 4k 1 2k 2 1k 4 512 8 512 9 256 16 256 18 128 32 128 36 64k 8 64k 9 32k 16 32k 18 16k 32 16k 36 8k 64 8k 72 4k 128 4k 144 parity bits vv byte enable vv pack mode vv address clock enable vv single-port memory vv simple dual-port memory vv true dual-port memory vv embedded shift register v ? rom v ? fifo buffer vv simple dual-port mixed width support vv true dual-port mixed width support vv memory initialization file ( .mif ) (1) ? mixed-clock mode vv power-up condition outputs unknown outputs unknown register clears output register s only output registers only same-port read-during-write new data available at positive clock edge new data available at positive clock edge
8?26 altera corporation september 2008 hardcopy series handbook, volume 1 pll planning and utilization stratix ii devices support enhanced plls and fast plls. hardcopy ii devices also support enhanced pl ls and fast plls, but with two variations: hardcopy ii devices have a different number of plls than stratix ii devices. hardcopy ii devices may support fewer i/o standards for clock inputs and outputs. this is expl ained in the i/o standards support section later in this chapter. table 8?18 shows which plls each hardcopy ii and stratix ii device supports. the stratix ii reference columns are divided based on package, not density. figures 8?3 to 8?5 show pll number designations. the stratix ii devices support 6 or 12 plls depending on the package offering, and not the device density. the hardcopy ii plls are not removed symmetrically from all four sides. in general, fast plls are removed from sides that do not support high speed ioes since the primary use of the fast pll on the sides is for high speed i/o interface functions. mixed-port read-du ring-write outputs set to unknown or old data unknown output power down of unused ram blocks (2) vv notes to ta b l e 8 ? 1 7 : (1) stratix ii m4k blocks support .mif file loading. (2) stratix ii memory blocks remain powered up even when not used. table 8?17. hardcopy ii embedded memory features (part 2 of 2) feature m4k blocks m-ram blocks table 8?18. stratix ii / hardcopy ii companion de vice pll availability guide (part 1 of 2) stratix ii and hardcopy ii companion devices package fast plls enhanced plls 123478910561112 ep2s30 hc210 (1) 484-pin fineline bga vv vv ep2s60 hc210 (1) 484-pin fineline bga vv vv ep2s90 hc210 (1) 484-pin fineline bga vv vv ep2s60 hc220 (1) 672-pin fineline bga vv vv
altera corporation 8?27 september 2008 preliminary pll planning and utilization hardcopy ii plls are functionally id entical to the st ratix ii plls. the hardcopy ii enhanced and fast plls support reconfiguration and are also reconfigurable for bandwidth and phase shift. figures 8?3 to 8?5 show the pll locations for each hardcopy ii device. for hc210 and hc220 devices, fast plls 1 and 2 are located in the logic array of the device and enhanced plls 5 and 6 are located in the periphery next to the device?s top and bottom i/o banks. ep2s90 hc220 (1) 780-pin fineline bga vv vv ep2s130 hc220 (1) 780-pin fineline bga vv vv ep2s90 HC230 (2) 1,020-pin fineline bga vv vv vvvv ep2s130 HC230 (2) 1,020-pin fineline bga vv vv vvvv ep2s180 HC230 (2) 1,020-pin fineline bga vv vv vvvv ep2s180 hc240 1,020-pin fineline bga vvvvvvvvvvvv ep2s180 hc240 1,508-pin fineline bga vvvvvvvvvvvv notes to table 8?18 : (1) hc210 and hc220 devices do not support fast p lls 3, 4, 9, and 10, unlike stratix ii devices. (2) HC230 devices do not support fast plls 3 and 4, unlike stratix ii devices. table 8?18. stratix ii / hardcopy ii companion de vice pll availability guide (part 2 of 2) stratix ii and hardcopy ii companion devices package fast plls enhanced plls 123478910561112
8?28 altera corporation september 2008 hardcopy series handbook, volume 1 figure 8?3. hc210 and hc220 pll locations HC230 device fast plls 1, 2, 7, and 8 are located in the logic array, next to the device?s left high-speed ioes. hc 230 device enhanced plls 5, 6, 11, and 12 are also located in the logic array, next to the top and bottom memory interface ioes. fpll10clk fpll9clk clk[8..11] fpll7clk fpll8clk clk[3..0] clk [ 7..4 ] clk[15..12] bank 4 memory interface ioes pll 5 bank 9 bank 7 general purpose ioes bank 8 general purpose ioes pll 6 bank 10 bank 3 memory interface ioes bank 2 high-speed ioes bank 1 high-speed ioes bank 5 general-purpose ioe s bank 6 general-purpose ioe s pll 1 pll 2
altera corporation 8?29 september 2008 preliminary pll planning and utilization figure 8?4. HC230 pll locations hc240 device fast plls 1, 2, 7, and 8 are located in the logic array, next to the left high speed ioes of the device. hc240 device fast plls 3, 4, 9, and 10 are located in the logic array, ne xt to the right high speed ioes. hc240 device enhanced plls 5, 6, 11, and 12 are located in the logic array, next to the top and bottom memory interface ioes. fpll10clk fpll9clk clk[8..11] fpll7clk fpll8clk clk[3..0] clk[7..4] clk[15..12] bank 4 memory interface ioes bank 7 memory interface ioes bank 8 memory interface ioes bank 3 memory interface ioes bank 2 high-speed ioes bank 1 high-speed ioes bank 5 general-purpose ioe s bank 6 general-purpose ioe s pll 1 pll 2 pll 7 pll 8 pll 5 pll 11 bank 11 bank 9 pll 6 pll 12 bank 12 bank 10
8?30 altera corporation september 2008 hardcopy series handbook, volume 1 figure 8?5. hc240 pll locations global and local signals hardcopy ii devices have 16 clock pins ( clk[15..0] ) to drive either the global or local clock networks. four clock pins drive each side of the device. this is similar to stratix i i devices; therefore, there are no limitations when compiling designs for stratix ii devices and hardcopy ii companion devices. internal logic and enhanced and fast pll outputs can also drive the global and regional clock networks . each global and regional clock network has a clock control block, wh ich controls the selection of the clock source and allows you to dynami cally enable or disable the clock network to reduce power consumption. fpll10clk fpll9clk clk[8..11] fpll7clk fpll8clk clk[3..0] bank 4 memory interface ioes bank 7 memory interface ioes bank 8 memory interface ioes bank 3 memory interface ioes bank 2 high-speed ioes bank 1 high-speed ioes bank 5 high-speed ioe s bank 6 high-speed ioe s pll 1 pll 2 pll 4 pll 3 pll 10 pll 9 pll 7 pll 8 pll 5 pll 11 bank 11 bank 9 pll 6 pll 12 bank 12 bank 10 clk[7..4] clk[15..12]
altera corporation 8?31 september 2008 preliminary stratix ii alm adaptation into hardcopy ii logic table 8?19 lists the clock resources available in hardcopy ii devices. stratix ii alm adaptation into hardcopy ii logic the basic logic building block in the stratix ii architecture is the alm. each alm contains a variety of look-up table- (lut-) based resources, two programmable registers, two de dicated full adders, and various routing resources to and from the alm. hardcopy ii devices do not have alm blocks, but us e a fine-grain architecture called hcells. hcells can implement all combinations of stratix ii alm and dsp logic. each hardcopy ii companion device contains an abundance of hcells to implement a st ratix ii design utilizing all available alms. therefore, there are no compatibility constraints when compiling for hardcopy ii devices. when compiling a stratix ii design into a hardcopy ii companion device, the quartus ii software replaces alm blocks used in stratix ii with predefined hcell macros. unused alm resources are not implemented in hardcopy ii devices. this allows for optimal placement of the hardcopy ii floor plan and significant power savings. figure 8?6 shows an example of a stratix ii alm block implementation using only one of the registers. when compiling this stratix ii design for a hardcopy ii companion device, the quartus ii compiler replaces the table 8?19. clock network resources and features available in hardcopy ii devices resources and features availability number of global clock networks 16 number of regional clock networks 32 global clock input sour ces clock input pins, pll outputs, logic array regional clock input s ources clock input pins , pll outputs, logic array number of unique clock sources in a quadrant 24 (16 global clocks and 8 regional clocks) number of unique clock sources in the entire device 48 (16 global clocks and 32 regional clocks) power-down mode global and regional clock networks, dual-regional clock region clocking regions for high fan-out applications quadrant region, dual-regional, entire device via global or regional clock networks
8?32 altera corporation september 2008 hardcopy series handbook, volume 1 alm block with a predetermined hcell macro that implements a register from its hardcopy ii library of hc ell macros. this macro entry has predetermined timing. figure 8?6. stratix ii alm simple registered input and output figure 8?7 shows a hardcopy ii alm regi ster implementation showing clock, data in, and data out originat ing from a small cluster of hcells. unused hcells are reserved for other logic implementation or powered down. figure 8?7. hardcopy ii unused hcells prn reg0 dq adder0 adder1 combinational logic dataf0 datae0 dataa datab datac datad datae1 dataf1 prn reg1 dq shared_arith_out carry_out reg_chain_out reg_chain_in carry_in shared_arith_in to general or local routing to general or local routing to general or local routing to general or local routing
altera corporation 8?33 september 2008 preliminary hardcopy ii dsp implementation from stratix ii dsp blocks hardcopy ii dsp implementation from stratix ii dsp blocks stratix ii fpgas have dedicated ds p blocks to implement various dsp functions. stratix ii dsp bloc ks consist of multipliers, an adder/subtractor/accumulator an d a summation block, input and output interfaces, and in put and output registers. the quartus ii software implements dsp functions in hardcopy ii devices with hcells using predetermined logic implementations from its library of hcell macros, all of which have predetermined timing. dsp blocks that are not used in the stratix ii design are not implemented in hardcopy ii devices. this preserves the hardcopy ii logic for other implementations, saving resource s and power. furthermore, the hardcopy ii dsp block placement can be optimized to meet the timing constraint requirements placed on the hardcopy ii designs. the hardcopy ii dsp implementation is functionally equivalent to stratix ii dsp blocks and all features are supported except for dynamic-mode switching. you can set up stratix ii dsp blocks to dynamically switch between the following three modes: up to four 18-bit independent multipliers up to two 18-bit multiplier-accumulators one 36-bit multiplier hardcopy ii dsp implementation does not support dynamic switching. if this feature is used, the quartus ii software flags the dsp implementation and does not allow you to migrate the design. the fitter reports that all hardcopy ii devices are not compatible with the design. to migrate your stratix ii design to a hardcopy ii companion device, disable dynamic switching in the dsp blocks. the total number of dsp blocks is dependent on the stratix ii device selected. hardcopy ii devices will match the available dsp block resources in the stratix ii device. table 8?20 lists available dsp implementations base d on the selected stratix ii device. table 8?20. dsp multiplier availability for stratix ii and hardcopy ii companion devices (part 1 of 2) stratix ii device hc210 hc220 HC230 hc240 9 9 18 18 36 36 9 9 18 18 36 36 9 9 18 18 36 36 9 9 18 18 36 36 ep2s30 128 64 16 ep2s60 288 144 36 288 144 36 ep2s90 (1) 384 192 48 384 192 48 384 192 48 ep2s130 (1) 504 252 63 504 252 63
8?34 altera corporation september 2008 hardcopy series handbook, volume 1 figure 8?8 shows an example of a stratix ii dsp block that uses only 1 of 8 available 9 9 multiplier blocks an d an accumulator block to implement an 8 8 bit multiplication function with clock latency. when this dsp block is implemented in the hardcopy ii design, the quartus ii compiler chooses the appropriate entry from the macro library to implement the 9 9 multiplier and accumulator block which results in an optimized logic utilization and placement flexibility. figure 8?8. hardcopy ii floor plan of 8 8 dsp block ep2s180 (1) 768 384 96 768 384 96 note to table 8?20 : (1) if these stratix ii devices are selected with smaller hard copy ii companion devices, all stratix ii dsp resources may not be available if all the stratix ii alm blocks are us ed and fully utilized. quartus ii will determine available resources for dsp and alm implementation wh en compiling with hardcopy ii devices. table 8?20. dsp multiplier availability for stratix ii and hardcopy ii companion devices (part 2 of 2) stratix ii device hc210 hc220 HC230 hc240 9 9 18 18 36 36 9 9 18 18 36 36 9 9 18 18 36 36 9 9 18 18 36 36
altera corporation 8?35 september 2008 preliminary jtag bst and extended functions figure 8?9 shows quartus ii floor plans of a stratix ii dsp block on the left and a hardcopy ii dsp implementa tion on the right, both configured with an 18 18 multiply with accumu late function. in the hardcopy ii implementation, the quar tus ii software selected the appropriate dsp logic implementation from the macro library which results in an optimal utilization of the hardcopy ii device?s hcells. the unused sections of the stratix ii dsp block remain powere d up, but these are not implemented in the hardcopy ii device. unused logic in hardcopy ii devices are powered down. figure 8?9. hardcopy ii floorplan of 18 18 dsp block jtag bst and extended functions hardcopy ii devices support the same boundary-scan test (bst) functionality as the stratix ii de vices. however, since hardcopy ii devices are mask-programmed, no reconfiguration is possible. therefore, hardcopy ii devices do not support instructions to reconfigure the device through the jtag pins. for a list of supported features and instruction codes, refer to the boundary-scan support chapter of the hardcopy series handbook . one stratix ii feature utilizing jtag pins is the signal tap ii embedded logic analyzer (ela). hardcopy ii devices support the jtag ela feature. however, designing with this feature will use additional resources and may reduce peak performance in stratix ii and
8?36 altera corporation september 2008 hardcopy series handbook, volume 1 hardcopy ii devices. unlike stratix ii devices, where this feature can be eliminated prior to compiling a final version of the design, hardcopy ii devices are masked programmed and this feature will remain permanent in the hardcopy ii device. therefore, if the design requires optimal performance and resource utilizatio n, altera recommends using this feature on the stratix ii prototype device, but eliminating it prior to recompiling the design for a hardcopy ii device. power up and configuration compatibility when designing a board with a stra tix ii prototype device and its companion hardcopy ii device, most configuration pins required by the stratix ii device are not required by the hardcopy ii device. to maximize i/o pin counts with hard copy ii device utilization, altera recommends minimizing power up and configuratio n pins that will not carry over from a stratix ii device into a hardcopy ii device. table 8?21 lists the dedicated and optional configuration pi ns that a stratix ii device can use and if their optional functionality is used on a hardcopy ii device. if the hardcopy ii device can use th e pin?s optional function found in stratix ii devices, the quartus ii soft ware allows you to set these pins as dual purpose pins. as du al purpose pins, they have i/o functionality after power up, reconfiguration and initialization. these pins will only switch to their i/o designation when the device enters user mode (when init_done is asserted). the design may require that some signals be present when the device transitions into user mode, so you should not use dual purpose pins because it may result in unstable operation after power up for both the hardcopy ii and the stratix ii devices. table 8?21. power up and configurat ion pin compatibility (part 1 of 3) stratix ii pin name i/o bank hardcopy ii use main function optional function main function optional function msel3 b4 msel2 b4 msel1 b4 msel0 b4 vccsel b8 vv n config b8 vv n status b3 vv conf_done b3 vv n ce b3 vv
altera corporation 8?37 september 2008 preliminary power up and configuration compatibility n ceo b7 vv porsel b7 vv n io_pullup b7 vv pll_ena b7 vv i/o pin clkusr b8 v i/o pin dev_oe b8 vv i/o pin dev_clrn b8 vv i/o pin init_done b3 vv dclk b3 v i/o pin data0 b3 v i/o pin data1 b3 v i/o pin data2 b3 v i/o pin data3 b3 v i/o pin data4 b3 v i/o pin data5 b3 v i/o pin data6 b3 v i/o pin data7 b3 v i/o pin rdynbsy b3 v i/o pin crc_error b3 v i/o pin cs b8 v i/o pin n cs b8 v i/o pin n rs b8 v i/o pin n ws b8 v i/o pin runlu b8 v i/o pin pgm2 b3 v i/o pin pgm1 b3 v i/o pin pgm0 b3 v table 8?21. power up and configurat ion pin compatibility (part 2 of 3) stratix ii pin name i/o bank hardcopy ii use main function optional function main function optional function
8?38 altera corporation september 2008 hardcopy series handbook, volume 1 most optional configuration pins listed in table 8?21 support the various configuration schemes available in stratix ii fpgas. parallel programming and remote update configuration modes utilize most of the pins in table 8?21 . hardcopy ii devices are not configurable and do not support the configuration emulation mode. therefore, altera recommends that you minimize the configuration pin requirements of the stratix ii design; for example, by using the passive serial configuration mode. if some of these dual-purpose pins are needed to configure the stratix ii fpga, but will be unused after configuration, these pins will be completely unused on the hardcopy ii device. therefore, when migrating from the stratix ii device to the hardcopy ii device, care must be taken when designing these pins on board. the removal of the stratix ii device and its corresponding configuration device may leave these pins floating on th e hardcopy ii device if su ch pins are assigned as inputs by the user, without any extern al means of driving them to a stable level. when selecting a stratix ii device and its device options, consider the after-configuration requirements of these pins and set them appropriately in the quartus ii software ( figure 8?10 ). i/o pin asdo b3 v i/o pin n cso b3 v table 8?21. power up and configurat ion pin compatibility (part 3 of 3) stratix ii pin name i/o bank hardcopy ii use main function optional function main function optional function
altera corporation 8?39 september 2008 preliminary conclusion figure 8?10. device and pin options f for more information about hardcopy ii power-up modes, refer to the power-up modes and configuration em ulation in hardcopy series devices chapter of the hardcopy series handbook . conclusion hardcopy ii devices provide a seamless migration path for stratix ii devices and supports the pll, memory, logic, and i/o features offered on a stratix ii device. the hardcopy ii de vice architecture also allows you to use a wide range of stratix ii de vices for prototypi ng. hardcopy ii devices offer pin-to-pin compatibilit y with stratix ii fpgas, making hardcopy ii devices drop-in replacem ents on systems designed with the quartus ii software and using stra tix ii and hardcopy ii companion devices. use the quartus ii software to compile designs and determine available resources to guarantee fit an d feature compatibility for stratix ii and hardcopy ii companion devices.
8?40 altera corporation september 2008 hardcopy series handbook, volume 1 more information for more information on migrating stratix ii designs to hardcopy ii devices, refer to the following sources: hardcopy ii device family data sheet in the hardcopy series handbook quartus ii support for hardcopy ii devices power-up modes and configuratio n emulation in hardcopy series devices chapter in the hardcopy series handbook document revision history table 8?22 shows the revision history for this chapter. table 8?22. document revision history date and document version changes made summary of changes september 2008, v1.4 updated chapter number and metadata. ? june 2007 v1.3 changed ?8k x 64? to ?16k x 36? in table 8?17 .? completed typographical updates. ? december 2006 v1.2 added revision history. ? march 2006 formerly chapter 19; no content change. ? october 2005 v1.1 minor edits ? may 2005 v1.0 added document to the hardcopy series handbook .?

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